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We were looking for a very specific type of ADC in a small package for one of our projects, and found something suitable in a TSSOP. We wanted to save more space, so looked into getting bare dies; the manufacturer confirmed the dies are 2mm square, but said we'd have to order "some millions" to make it worth providing them. We needed maybe 500/yr and the budget is not huge, so that was the end of it and we decided to do something else.

But I was curious: What do people do when they want small numbers of bare dies? Does anyone decap ICs and use the dies in production? If so, can the process be made reliable, and roughly how expensive is it?

If anyone has examples of products or case studies, that would be really interesting.

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    \$\begingroup\$ Not an answer, just a caveat - semiconductors can be light sensitive: Raspberry Pi Xenon Death Flash. \$\endgroup\$ – Andrew Morton Oct 13 '18 at 14:26
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    \$\begingroup\$ If there are a sufficient number of low volume buyers for a product that a manufacturer does not want to deal with, a wholesaler will buy large volume lots and resell to low-volume customers. If there is not a sufficient volume, potential customers "do something else." \$\endgroup\$ – Charles Cowie Oct 13 '18 at 14:35
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    \$\begingroup\$ @AndrewMorton In this hypotehtical case, the die would be stuck to a PCB along with some other components, then encapsulated. So that shouldn't be a problem. I wouldn't want to leave the bare die open anyway, as the wirebonds will be very fagile. \$\endgroup\$ – Jack B Oct 13 '18 at 14:54
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    \$\begingroup\$ I would say designers first seek out CSP parts like bga before trying to get bare die. \$\endgroup\$ – sstobbe Oct 13 '18 at 14:55
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    \$\begingroup\$ @sstobbe BGA would be much nicer and easier than bare die, but the manufacturer definitely isn't going to do that for us. Whereas at least in theory, smaller numbers could be decapped from the readily available TSSOP. Hence me wondering if anyone did that. \$\endgroup\$ – Jack B Oct 13 '18 at 14:58
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I can't speak for all manufacturers or all product lines, but I've worked as an applications engineer at Maxim Integrated Products for 25+ years.

You mention that the product in question is some kind of ADC, so there will be lots of internal adjustments performed after packaging, during the final test. (e.g. bias trim, reference adjustment, linearity, etc.) And that post-packaging final test program uses secret "test mode" commands, which are company confidential. (If you were a primary/strategic/key customer those might be available under NDA, but you'd be having that conversation with the business manager, not me.)

Decapping the chip out of a TSSOP and ripping it off of the leadframe (typically a conductive epoxy bond) will definitely subject the chip to mechanical stresses beyond its design limits. This will very likely degrade its performance, permanently. Modern IC design uses MEMS technology to relieve mechanical stresses which are internal to the package, those mechanical forces on the chip would otherwise degrade performance. If you're trying to get decent 20-bit (or even 12-bit) performance from an ADC chip, subjecting it to that kind of mechanical violence could ruin its linearity, making the whole exercise futile.

You might be able to get away with decapping a pure digital chip, but for precision analog I would strongly urge you to reconsider. I just now looked at our online product selector guide (precision ADCs) and found a few 12-bit/16-bit SAR ADC which are smaller than 4mm2 (the only requirement you mentioned). This includes WLP Wafer Level Packged parts, which is pretty close to bare die, but just a little bit nicer to deal with.

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    \$\begingroup\$ Thanks, that's very interesting. It's actually a ΣΔ capacitance-to-digital converter we were looking at, which cuts our packaging options considerably. We would hypothetically trim the leadframe down rather than trying to get rid of the die attach epoxy. I hadn't realised how strain sensitive the chips could be though, from the sound of it even messing with the wirebonds could introduce too much strain. \$\endgroup\$ – Jack B Oct 14 '18 at 10:37
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I have used de-capped IC in pico-probing for silicon debugging. (Where you remove the top and passivation layer and then put probe needles on the die) The decapping is done with special hot-acid pump and a special rubber 'window'. The idea of decapping is to have a more or less complete package but have access to the silicon.

  1. You save no space. You have the whole package but just with a hole at the top.

  2. The bond wires where still there, so no clean die.

You could try throwing a bundle of chips in boiling acid and see what comes out. But my guess is the bond pads will not be usable anymore.

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  • \$\begingroup\$ I'm aware of this type of decapping process, and as you say it doesn't save us any space. I could try the boiling acid approach but I expect it would rip the wirebonds off. Maybe ultimately I could get a working die to use in a prototype, but I'm really interested to know if anyone has a process/service that can do it reliably enough for production. \$\endgroup\$ – Jack B Oct 13 '18 at 21:45
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The manufacturer won't make a new package variant on its own since it has to do all characterization again. It cannot guarantee the same specifications in a different package, this requires testing and validation.

They might be willing to do this at a smaller scale, at a higher price to offload the risk.
You will need to pay upfront, or sign contracts.

Decapping to recover dies is not the only step. You also have to remove it from the leadframe, which is glued. And re-do the wire bonding.

leadframe qfp

Removing wire-bonding is something I have not heard of before.

The amount of specialty equipment and skill required to develop and perform this operation will be significant.

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  • \$\begingroup\$ I recon if I could get a handful of chips looking like that, I could do a decent job of using one in a prototype. We'd probably go round cutting the wirebonds close to the leadframe, then trim away the leadframe with a slurry saw or similar. If there's space to bond new wires on the wirebond pads, great, if not then we might be able to bend the existing ones down and connect them to a PCB with die attach epoxy. The yield wouldn't be anywhere near good enough for production though. I was really wondering if anyone knew of a process/service which would give good yields. \$\endgroup\$ – Jack B Oct 13 '18 at 22:06
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I believe IS I or Quik-Pak may be able to work with you for repackaging, and they are both used to smaller volume customers. Another poster pointed out a potential show-stopper, the factory tuning on the ADC. Depending on the specs of the ADC, the packaging may be codesigned with the IC. The new package may require careful attention to achieve the specs of the original.

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