VHDL Output is Unitiliazed or Zero when simulated

Question

I am new to VHDL and implementing a test bench. I am trying to write code for a simple 2:1 MUX where the output of the MUX enters an active high synchronous LOAD register. Inputs and outputs are 8 bits. When I run my simulation my output F reads 'U'. I also tried to initialize the output signal in the test bench to (others => '0') but that just makes my output F = 0. Any help would be greatly appreciated, thank you!

DESIGN

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity REG_A is
    Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
           B : in STD_LOGIC_VECTOR (7 downto 0);
           SEL : in STD_LOGIC;
           LDA : in STD_LOGIC;
           CLK : in STD_LOGIC;
           F : out STD_LOGIC_VECTOR (7 downto 0));
end REG_A;

architecture Behavioral of REG_A is
    signal s : std_logic;
    signal s_mux_result : std_logic_vector(7 downto 0);

begin

    regA : process (CLK)
    begin
        if (rising_edge(CLK)) then
            if (LDA = '1') then
                F <= s_mux_result;
            end if;
        end if;
    end process;   

    with s select
    s_mux_result <= A when '1',
                    B when '0',
                    (others => '0') when others;

end Behavioral;

TEST BENCH

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity regA_tb is
end regA_tb;

architecture Behavioral of regA_tb is
--INPUTS
signal A : std_logic_vector(7 downto 0) := "01100101";
signal B : std_logic_vector(7 downto 0) := "11100111";
signal LA,SEL : std_logic;
signal CLK : std_logic := '0';

--OUTPUT
signal F : std_logic_vector(7 downto 0):= (others => '0');

component regA
    port( 
        A,B: in std_logic_vector(7 downto 0);
        LA,SEL : in std_logic;
        CLK : in std_logic := '0';
        F : out std_logic_vector(7 downto 0)
        );
end component;


begin
dut: regA port map( A => A, B => B, LA => LA, SEL => SEL, CLK => CLK, F => F);

    --GENERATE CLOCK
    generate_clock  : process 
    begin
        wait for 50 ns;
        CLK <= '1';
        wait for 50 ns;
        CLK <= '0';
    end process;

    switch_process : process
    begin
        SEL <= '0';
        LA <= '1';
        wait for 100 ns;
        SEL <= '1';
        LA <= '1';
        wait for 100 ns;
    end process;
end Behavioral;

Answer 1

You have made an architecture for "reg_A" but try to instantiate a component "dut" with definition name "rega" meanwhile such component is not exists in your generated library(work). You also did not connect the "SEL" of the entity port to local defined "s" that most probably is a typing mistake.

I have changed your code and it seems that its simulation is working properly now.

The changed code is this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity REG_A is
    Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
           B : in STD_LOGIC_VECTOR (7 downto 0);
           SEL : in STD_LOGIC;
           LDA : in STD_LOGIC;
           CLK : in STD_LOGIC;
           F : out STD_LOGIC_VECTOR (7 downto 0));
end REG_A;

architecture Behavioral of REG_A is
    signal s : std_logic;
    signal s_mux_result : std_logic_vector(7 downto 0);

begin

    regA : process (CLK)
    begin
        if (rising_edge(CLK)) then
            if (LDA = '1') then
                F <= s_mux_result;
            end if;
        end if;
    end process;   
    s <= SEL; --changed by BD_CE
    with s select
    s_mux_result <= A when '1',
                    B when '0',
                    (others => 'Z') when others; --changed by BD_CE

end Behavioral;

The changed test bench is:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity regA_tb is
end regA_tb;

architecture Behavioral of regA_tb is
--INPUTS
signal A : std_logic_vector(7 downto 0) := "01100101";
signal B : std_logic_vector(7 downto 0) := "11100111";
signal LA,SEL : std_logic;
signal CLK : std_logic := '0';

--OUTPUT
signal FOUT : std_logic_vector(7 downto 0); --changed by BD_CE

component REG_A  --changed by BD_CE
    Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
           B : in STD_LOGIC_VECTOR (7 downto 0);
           SEL : in STD_LOGIC;
           LDA : in STD_LOGIC;
           CLK : in STD_LOGIC;
           F : out STD_LOGIC_VECTOR (7 downto 0)
          );
end component;

begin
dut: REG_A port map( A => A, B => B,SEL => SEL, LDA => LA,  CLK => CLK, F => Fout); --changed by BD_CE

    --GENERATE CLOCK
    generate_clock  : process 
    begin
        wait for 50 ns;
        CLK <= '1';
        wait for 50 ns;
        CLK <= '0';
    end process;

    switch_process : process
    begin
        SEL <= '0';
        LA <= '1';
        wait for 100 ns;
        SEL <= '1';
        LA <= '1';
        wait for 100 ns;
    end process;

end Behavioral;