# SDC constraints for reusable component

I have a simple register based clock divider component I can drop in when I don't have a spare PLL:

library IEEE;

use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;

entity div128 is
port(
inclk0 : in std_logic;
locked : out std_logic;
c0 : out std_logic
);
end entity;

architecture syn of div128 is
begin
div : process(inclk0) is
variable counter : unsigned(6 downto 0);
begin
if(rising_edge(inclk0)) then
counter := counter + 1;
c0 <= counter(6);
end if;
end process;

locked <= '1';
end architecture;


Now I'd like to reuse this component in multiple places, in different clock domains, without repeating myself more often than strictly necessary.

• Do I need to create a create_generated_clock statement for each instance, or can I specify once that each instance generates a -divide_by 128 clock from its input?

• Could I also pull the divider from a generic parameter and take it over into the timing constraints?

• Would it make sense to use attributes here instead of an SDC file?

You can specify SDC commands inside of your VHDL code with ALTERA attributes. The PoC Library is using this to apply relative timing constraints for synchronizers:

architecture rtl of sync_Bits_Altera is
attribute ALTERA_ATTRIBUTE  : string;

-- Apply a SDC constraint to meta stable flip flop
attribute ALTERA_ATTRIBUTE of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to [get_registers {*|sync_Bits_Altera:*|\gen:*:Data_meta}] """;
begin


I think you could do a similar approach for your generated clock.

Please note, that c0 does not fulfill all requirements to be a clock signal.

• I'm getting a warning from TimeQuest that c0 is not defined as a clock, even though it is used as one. It is probably not usable as a PLL input anymore (but neither is coreclk_out from the PCIe block, which is why I have so many clock domains in the first place. – Simon Richter Oct 22 '18 at 6:43