Why do we need to set speed for GPIO output pins in STM32?

The STM32F4 Reference Manual on page 278 says that:

The data present on the I/O pin are sampled into the input data register every AHB1 clock cycle.

Then why do we need to set speed to the pins while it is specified?.

  • Welcome to EE.SE. – Sparky256 Oct 14 at 22:30
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    Hello Amin! Please see this related question. – bitsmack Oct 15 at 1:09
up vote 8 down vote accepted

STM32F4-Refrence Manual in page 278 says that "The data present on the I/O pin are sampled into the input data register every AHB1 clock cycle"

This text is referring to input pins, not outputs.

The output speed register only affects pins which are configured as outputs. It controls the slew rate (drive strength) used for the output. Using an excessively high speed may cause ringing and EMI on outputs, so it is important to use the minimum speed required for your application.

  • Inputs as well. It is guaranteed that the change of the input pin by the external world will propagate as quiche as the bus speed. – P__J__ Oct 15 at 1:01
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    @P__J__ I'm confused what you're trying to say here. The GPIO speed settings affect slew rate, not clock rate. They do not have any effect on GPIOs which are not configured as outputs. – duskwuff Oct 15 at 2:31

Most any very fast CPU or MPU have bus or GPIO pin speeds that require 10 ohm to 27 ohm resistors in series at the endpoint of the trace to prevent ringing and adjacent trace cross talk. If your GPIO data or IO control is erratic then maybe you have to slow down AHB1 rate or insert those resistors I mentioned.

If pin is an input then resistor is at the pin. If the pin is an output then resistors is at the device pin being driven. Dampening or impedance matching resistors might allow you to keep current AHB1 speed. If you still have data corruption then you MUST slow down the AHB1 rate or insert a few nops or wait-states to throttle back the IO speed

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    Pretty sure that anything that can be accomplished by changing the bus clock can also be done by inserting wait states... so stating "you MUST slow down the AHB1" isn't accurate. – Ben Voigt Oct 15 at 3:54
  • @Benvoight. I added that to my answer. – Sparky256 Oct 15 at 13:21
  • That whole line of thought is mistaken. It has nothing to do with the bus speed, but rather with the driver slew rate. And the speed settings the question refers to are slew rate control bits of those drivers, not external resistors. – Chris Stratton Oct 15 at 14:51
  • @ChrisStratton. Ok, so I missed the OP's point, but series resistors are still use on every motherboard with very fast bus speeds, sometimes at both ends. Even with slew rate control the resistors dampen ringing and to some degree act as impedance matching devices so optimum speed without corruption is possible. – Sparky256 Oct 15 at 18:44

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