I am really confused by the conception of net type, variable type, data type and data objects in SystemVerilog. I am using the simulator inside Xilinx Vivado 2018.02 for all the following codes.

logic in SystemVerilog can partially substitute the role of wire in Verilog. Say I have the following code within a module

logic q_bar;
logic q;
assign q_bar = ~q;
always_ff @(posedge clk or negedge rst) begin
        q <= 1'b0;
        q <= q_bar;

Does the compiler infer a net type for q_bar since we assigned it? q is of variable type since its assignment is in a procedural block. Another example:

typedef logic [7:0] mem_t[3:0][3:0];
typedef wire [7:0] byte_wire_t;

The first line is legal, but the simulator complains about the second one: "SystemVerilog keyword wire used in incorrect text". But the grammar of typedef is

typedef data_type type_identifier { variable_dimension } ;
| typedef [ enum | struct | union | class | interface class ] type_identifier ;

Isn't wire a data type? Is net type a data type?


1 Answer 1


No wire is not a data type; it is a net type. SystemVerilog has some confusing implicit declaration defaults to be backward compatible with Verilog.

When you write the following in Verilog:

wire w;

it's the same as this following in SystemVerilog:

wire logic w;

This means w is a net with a 4-state data type (0,1,x or z). And the wire kind of net means it can have multiple drivers with different strengths. When there are conflicting states with the same strength, the net resolves to the X state. Other kinds of net types use AND or OR to resolve conflicts. Net types cannot have procedural assignments.

When you write the following declaration in Verilog:

logic v;

it's the same as this following declaration in SystemVerilog:

var logic v;

This means v is a variable with a 4-state data type (0,1,x or z). And being a variable means it is allowed to have only one continuous assignment, or any number of procedural assignments. It cannot have both kinds of assignments.

Whether a variable gets synthesized into a Register/flop or physical metal wire depends on its usage.

You may also want to read http://go.mentor.com/wire-vs-reg

BTW, there are slight differences in the defaults for module port declarations. For example (input logic w) defaults to a wire net type, not a variable.

  • \$\begingroup\$ "w is a net with a 4-state data type...". Could I understand it this way: data types could be attached to a net type or a variable type. For the net type, only a 4-state data type is allowed. For the variable type, both the 4-state and 2-state (logic and bit) are allowed. \$\endgroup\$
    – Harold H.
    Commented Oct 15, 2018 at 17:26
  • \$\begingroup\$ Yes. The built-in net types can only have 4-state data types, including struct, enum. For non-synthesizable code, variables can be any data type, i.e. real. \$\endgroup\$
    – dave_59
    Commented Oct 15, 2018 at 17:34

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