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In my book there is the architecture of a basic circuit with a half adder with 1 AND and 1 XOR for the carry, and a "maimed" half adder with one XOR for the previous carry. Then book say that minimum time of an operation is $$t_{min}=t_{xor} $$ (without carry) and the max time is $$t_{max} = t_{xor} + t_{and}$$ but the max time should not be $$t_{max} = 2t_{xor} + t_{and}$$ ?

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The output of the top XOR is not an input to the logic that generates D1, so the delay through the top XOR does not contribute to the delay from Q0 and Q1 to D1.

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Your "maimed" circuit makes no sense at all. A half-adder is just two gates:

schematic

simulate this circuit – Schematic created using CircuitLab

A full adder combines two half-adders and an OR gate to handle carry-in and generate carry-out:

schematic

simulate this circuit

If for some reason you wanted a circuit that had a carry-in but no carry-out, you'd simply eliminate all of the AND and OR gates:

schematic

simulate this circuit

There is no configuration that has an XOR gate following any AND or OR gate.

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  • \$\begingroup\$ The circuit was written by my professor of Electronics, I thought that it was right. \$\endgroup\$ – Lorenzoi Oct 15 '18 at 17:31

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