Hi I am new to the world of convolutional neural networks and would like to implement a 2D convolution operation using the sliding window approach on a xilinx FPGA. The input to the image is a 32x32 image with 2 channel on which 6 kernels of 5x5 is convolved to produce 6 output feature maps. Now assuiming I have sufficient DSPs on the FPGA, how would I parallelise the problem? After doing some research I have understood that we can either parallelise over the input or output feature maps or the kernel or both. For a 5x5 kernel, I would need 25 multiplications and 25 additions including the bias. If I have 25 DSPs operating in parallel, I can achieve this in one clock cycle. Is my understanding of the problem of parallelization correct up to now?
Now considering the input is stored in buffers and streamed to my convolution module and weights are pre loaded to the module, how is the sliding window computation performed? I realise I would have to use counters to keep track of the position of the input till the end of the N_W and N_H respectively. There is quite a lot of literature about implementing this using systolic arrays of multipliers but I am not sure I get those.
Could someone help me understand a dataflow for the convolution operation?
Any help would be greatly appreciated. An eager student.