I have a project involving an ADC sampling at 500 MHz. I need to take this ADC data and boil it down into something a cheap CPU can process. I believe this is a good application for a low-grade FPGA, so I am trying to understand how best to approach selecting a specific FPGA device.
The math involved in the FPGA will be minimal. Basically, I need the 500 MHz sampling speed to capture the physical event, but the FPGA will be selectively discarding most of the samples. So I don't think I care about how many LUTs, cells, or RAM bits the FPGA has. I need relatively fast I/O, and I need it to be cheap.
How can I tell if one of the cheap FPGAs (example: Spartan-6) I'm looking at is fast enough to keep up with my ADC? For the purposes of the this question, assume the ADC has an LVDS connection. Two ADC chips I am considering are the AD9434 and the ADS5403. I'm trying to understand the minimum requirements to interface with an ADC of this caliber.
What dictates the limit on an FPGA's I/O communication speed?
What are the key datasheet parameters I should be paying attention to when looking for an appropriate part?
Note that this is an embedded application, so stringing together some dev boards can be effective to prove out chip performance, but ultimately this will be a custom design.
Also note that the final sampling speed for future work may differ, so I am interested in understanding and comparing key I/O parameters between FPGAs in general. Other applications may require 250MHz sampling, or 1GHz, or 1.5GHz. I want to understand the FPGA I/O bottlenecks so I can choose a cost-effective FPGA for whatever sampling speed may be required.