I have a synthesizable Verilog/logical design question. My question is more logical than syntax.
I wish to implement some sort of router that has three input/output ports of full-duplex UART RS232, that are sending packets to each other.
Main points of design:
- The packets are with variable size and they contain the following fields: source(1 byte), destination(1 byte), payload length(2 bytes), payload.
- payload length is variable between 4-2000 bytes.
- I want to have some sort of routing table "what destination will be routed to which of the UART ports", and some sort of firewall(not sure the proper name) something like "which sources allowed to send packets to which UART ports".
- loopback is allowed (the packet that is received and sent through the same port)
- broadcasting is allowed (maybe destination address that routed to more than one UART port)
- the module needs to be generic so I could expand it to more than 4 ports.
For me, I think the hardest part to start with - is how to handle variable size packets? If the packets were fixed size, and not too big, I would have had an input FIFO and an output FIFO for each UART port:
reg [packet_size-1:0] fifo[num_of_packets]
each input FIFO would have stored in each fifo[I] a whole packet that was received from the uart, and a module that reads whole packets from each input FIFO, checks for source the dest of each packet and using that routes the packet to the wanted output FIFO,and from there a UART transmitter that takes a packet and sends it byte after byte. Problem is that a packet can be really really big, so I don't want to hold a fifo that has 2000 bytes in each cell...
That also brings the question of how to transfer the packets between the internal modules? As said, a packet can get really big.
I realize there are a lot of questions in my post, but I will much appreciate any help. Also, if there are some reference designs or something similar that can help me, I will happily review it.
Thanks for the help.