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I'm doing PCB layout for a USB 3.0 connection and I'm curious about if there's a length match requirement between the unidirectional super speed pairs and the bidirectional high speed pair. This isn't for a specific USB 3.0 driver or receiver, but what is considered good practice for operation.

For clarity I'm going to refer to the bidirectional high speed lines as BI+ and BI- and the unidirectional super speed lines as TX+, TX-, RX+ and RX-. What I have seen so far is listed below:

  • TX+, TX- lines should be within 5 mils (0.13 mm) of each other.
  • RX+, RX- lines should be within 5 mils (0.13 mm) of each other.
  • BI+, BI- lines should be within 50 mils (1.25 mm) of each other.
  • The TX pair and RX pair don't have any length requirement with respect to each other.

The length matching requirements in pairs make sense, but I'm not confident that the TX pair and RX pair don't have a length mismatch requirement for all devices. I'm also not sure if the BI pair has any length requirement with respect to the TX and RX pairs. Are there any general rules of thumb to follow for matching the lengths of pairs to other pairs to avoid errors?

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  • \$\begingroup\$ Welcome to EE.SE. The PIC32MZ datasheets only specify details of individual pairs, and suggest the port be within 75mm of the driver. Use round or 45 deg turns with ground plane between paired traces. But that was just Microchips own guidelines. \$\endgroup\$
    – user105652
    Oct 16 '18 at 21:46
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The length matching within each pair is very stringent, but as you have observed, there is no requirement for matching between different pairs. It makes sense, because the three pairs are used for very different things that do not need to be synchronized to each other. Any coordination of the traffic on different pairs is handled at a much higher level than the physical level.

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  • \$\begingroup\$ +1 Yes, that's right, Rx and Tx are nearly independent links and all protocol responses in USB3 totally asynchronous. You can also swap + and - wires in Rx/Tx diff.pairs if layout benefits from that. USB 3.x protocol is agnostic to signal polarity, and USB certification suite has an explicit test for this. \$\endgroup\$ Oct 22 '18 at 3:55

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