# Clock domain cross and metastablilty problem

I understand the problem of metastability and understand that we can't get a stable value in a bounded time so we need unbonded time but it is not practical,

so we put another flip flop with no logic to let a complete clock period be available to the metastable state to be stable state

But the metastable state is equally probable to be '0' or '1' as the mechanical analogy of a hill

so why after the ff synchronizer the stable value dout will be exactly equal to the input din ??

TL;DR; The circuit doesn't prevent the first register (the one connected to din) from going metastable. What it does do is reduce the probability that metastable value from propagating into the rest of the circuit.

Let's start with a 1-flop synchroniser. The register will clock in the value of din and align it to the clock edge. All good? not quite.

If din is still changing when the clock occurs, the output may go into a metastable state. If the output of this register is connected to other circuitry, this metastable state will propagate through the connected circuitry. Not good - this can lead to concurrency issues if multiple registers are fed from the same metastable signal, to incorrect values being generated from combinational logic, to state machines entering the wrong state.

What happens if we add a second register? The metastable state of the first can still occur. However the second register always (*) clocks the value one clock cycle later. As such there is now a time gap between the first register and the rest of the circuit.

If the first register goes metastable, but resolves to either 1 or 0 (it could be either) in less than one clock cycle, then by the time the second clock cycle occurs, there is no metastable state when second register samples the value. The propagation of the metastable value to the rest of the circuit has been prevented. There will as a result be either 1 or 2 clock cycles of delay as a result of the second register depending on what value the metastable state resolves to.

This massively reduces the probability that a metastable state will propagate - there is a mean-time before failure (MTBF) that can be calculated based on probabilities - for one register it could be as low as 1 clock cycle, for two registers it can be as long as the age of the universe.

Adding additional registers can further reduce the probability of metastability by catching any metastable values in the second register (in case the first register didn't resolve within a clock cycle). However there is a law of diminishing returns, which is why in most general designs you will see 2-flop synchronisers, and 3-flop in mission critical designs.

(*) assuming the clock is routed with minimal skew.

• It does not "prevent" the invalid state from propagating - it simply reduces the probability that it will. For high clock rates, and therefor small settling times, synchronizers will often use multiple stages in order to get the probability down to the desired level. Oct 17, 2018 at 17:58
• @WhatRoughBeast true - I did mention probability later on, but you're right the first sentence needed correcting. Oct 17, 2018 at 22:26
• And upvoted but deleted, is this (ex) answer:There are several variables in resolving metastability. a) bandwidth of the feedback loop; must be a lot faster (100 TAU) faster than the clocking period b) gain of the feedback loop c) random noise floor of the feedback loop d) deterministic noise floor (power supplies, trash from adjacent IC metallization) of the feedback loop Oct 18, 2018 at 3:05

Yes, if the metastable state occurs, it is equally likely to resolve to either 0 or 1. This really doesn't matter in the grand scheme of things, however.

Let's say that the asynchronous input makes a transition from 0 to 1, and this transition happens close enough to a clock edge to cause the first FF to go metastable.

• If the metastable state resolves to 1, then the second FF will also go to 1 one clock later, and all is good.

• If the metastable resolves to 0, the second FF will remain at 0 for one more clock cycle, but on that next clock cycle, the first FF will go to 1 (no metastability possible) and the second FF will go to 1 one clock after that.

In other words, the only effect of the metastability resolving the "wrong" way is to simply delay the transition at the output of the second FF by one clock. This is the same result that you'd get if the original input signal had been just a little bit later (with respect to the clock) to begin with. It has no effect on the operation of the system overall.

The point is, the second FF has a tremendously reduced probability of going metastable itself — this can only happen if the first FF goes metastable in the first place AND that metastability happens to resolve itself within a tight window around the next clock edge.

• so the function of the second FF is to prevent passing a metastable value to domain2 in the first clock cycle because after the first clock cycle the value will not be metastable right ? Oct 17, 2018 at 11:43

The key is understanding that metastable states will resolve themselves in a (probably) finite time. So the first stage aquires the data, and the second stage waits one clock period before attempting to grab it. The probability of a metastable state persisting for time t after the clock is typically some function of e^-t, so the longer the second waits the better the chance of grabbing valid data - and the likelihood of failure drops dramatically with time.

Of course, the probability never actually gets to zero, so synchronizers will have a specified BER (bit error rate). If the clock rate is high, the settling time is low, and in some cases is unacceptably low. In this case, the usual strategy is to add another flip-flop, or even more, depending on the numbers. This decreases the probability of error at the cost of adding latency time to the data.