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As per Miller effect the gate voltage stops to grow at the threshold level until some certain moment:

enter image description here

This can be explained as the drain to gate capacitance drives current through the gate. However - it is clearly can be seen on the picture that the flat area goes far beyond the moment Vds drops to the minimum. I could suppose that Vgs should grow further after 35 nC or so. But it stays still until 85 nC or so.

It is clear that dU/dt (which is the most important part in the equation of the capacitor current) much lower after 35 nC or so.

I checked several datasheets from different manufacturers but the picture is roughly the same.

So the question is:

What holds the gate for extra 50 nC (if we take this TK31V60W5 Toshiba MOSFET as the example)?

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    \$\begingroup\$ Perhaps some weird quantum mechanics. Even the simple semiconducor diode behaves weird, difficult to understand what's really happening. Go search Miller plateau, ... \$\endgroup\$ – Marko Buršič Oct 17 '18 at 20:22
  • \$\begingroup\$ To absorb charges, some voltage has to be changing. In your diagram, no voltage is changing. The diagram is faked. \$\endgroup\$ – analogsystemsrf Oct 18 '18 at 3:02
  • \$\begingroup\$ @analogsystemsrf even if the diagram is fake (I'm sure that in part it is true) it shows some critical points, which I hope is a experiment result. \$\endgroup\$ – Roman Matveev Oct 18 '18 at 5:20
  • \$\begingroup\$ The diagram is indeed mis-edited to some degree. Flat Vgs means charge absorbed and Vds must be changing for the whole flat Vgs spread. What is wrong is to believe the rate of change if Vds is constant as depicted in idealised diagrams In first approximation Crss rules this rate but this capacitance strongly depends on Vds itself, in this case it spans nearly 3 decades from 10s pF to several nF and same does to Vds Vs Qg slope. So in short at low Vds what seems a zero volt flat line on the right hand side of Miller plateau is instead a slow down slope \$\endgroup\$ – carloc Oct 18 '18 at 14:45
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MOSFET switching

Let's first approximately model MOSFET inductive load switching behaviour, far from a complete study on the topic I'll just recall main points and later on focus on the voltage slope period.

schematic

simulate this circuit – Schematic created using CircuitLab

Turn-on phase can be roughly divided into 4 sub-periods here depicted. International Rectifier AN-944

  1. Delay time (\$t_0,t_1\$), gate voltage exponentially rise while below threshold voltage, no drain current flowing, the whole load current is now circulating through freewheeling diode, drain is actually shorted to Vcc by this ON status diode.

  2. Current slope (\$t_1,t_2\$), when \$v_\text{GS}\$ crosses threshold \$i_\text{D}\$ begins to rise and starves freewheeling diode, when gate voltage and hence drain current is high enough to get diode current to zero freewheeling diode opens (disregard recovery), from now on \$v_\text{DS}\$ can change.

  3. Voltage slope (\$t_2,t_3\$), now MOSFET has drain current flowing and \$V_\text{DS}\$ can change, it is actually in active region and works like a high gain linear inverting amplifier. Its input (gate) and output (drain) happen to be shorted by \$C_\text{rss}\$ capacitance, this turns the whole stage in an inverting integrator, just the same as the one would build around an operational amplifier, gate voltage reamains constant to what is called Miller plateau.

  4. Gate top-up (\$t_3,t_4\$), when \$v_\text{DS}\$ approaches zero the MOSFET exits active region to enter ohmmic one, it is now fully ON, gate voltage completes its exponential rise from Miller plateau to \$V_\text{GS(on)}\$ as configured in the gate driver.

The turn-off can be roughly modelled simply inverting the above steps, from four to one.

I once more wish to clarify that all the above is just a very basic modelling of actual behaviour and the above graph is also a very simplified approximation and many condition can significantly change the above

Voltage slope

Let's come to the point recalled in the question, the following schematic applies.

On its left hand side we see:

  • \$i_\text{D}\$ has now reached the current flowing in the inductor (load) and hence freewheeling diode is open circuit now and has been removed.
  • Load inductor itself is modelled has a current generator since switching times are so faster than inductor dynamics not to let any current change happen.
  • \$v_\text{GS}\$ is now what is required to let exactly \$i_\text{D}\$ to flow, namely \$v_\text{GS,Miller}=V_\text{GS(Th)}+{i_\text{D}}/{G_\text{f}}\$. It remains constant since \$i_\text{D}\$ is also constant.
  • M1 MOSFET works like an inverting amplifier, current source and MOSFET output resistance are its load.

schematic

simulate this circuit

All the above resembles the inverting integrator depicted on the right hand side where rate of change of output voltage can be written as $$\frac{\text{d}v_\text{DS}}{\text{dt}}=-\frac{1}{C_\text{rss}}i_\text{G}=-\frac{1}{C_\text{rss}}\frac{\text{d}Q}{\text{dt}}$$

where Q is the charge "pumped" into the gate.

Rearranging a little bit we finally get to the relation $$\frac{\text{d}v_\text{DS}}{\text{d}Q}=-\frac{1}{C_\text{rss}}$$ needed to analize drain voltage slope in the \$v_\text{DS}\$/Q plane.

The answer

Now we have the tools, the graph originally posted shows a steep fall in the left hand side and a flat zero volt line immediately after.

This is basically wrong, drain voltage cannot be stand still as long as gate voltage is at Miller plateau. enter image description here

What is misleading is expecting \$C_\text{rss}\$ to be constant so to get one of those nice ideal graphs included in more or less all the application notes around.

Instead a quick look to the capacitance to drain voltage diagram enter image description here Clarifies that \$C_\text{rss}\$ spans over nearly three decades from 10pF at high voltages up to 4nF at low voltages.

This dramatically changes the \$v_\text{DS}\$ slope, it takes about \$10\,\text{pF}\times 350\,\text{V}=3.5\,\text{nC}\$ to get from 400V to 50V, while around \$2\,\text{nF}\times 20\,\text{V}=40\,\text{nC}\$ can be reckoned to span the last 20V or so.

One should admit that drawing a 1:400 slope difference on that linear-y graph is indeed a challanging task, overdoing a bit that's how it could look like. enter image description here

I'd end it up confirming such a phenomenon is clearly visible on real switching scope captures once you know where to look. enter image description here

(Just note this is a turn-off and hence it looks vertically flipped)

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That looks a bit suspicious. Certainly all the theoretical curves you can find show that the Miller plateau ends when Vds falls to its minimum, like this one from a IR datasheet,enter image description here

or this one from an Alpha and Omega datasheet

enter image description here

Real Vgs curves are never quite as crisp as these, so maybe these have been sanitized into neat three-line segment curves? This one, from a Toshiba app note seems to agree with the theoretical behavior.enter image description here

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  • \$\begingroup\$ Miller plateau is higher than Vthrs?! Another one big surprise for me. Question: is that correct that rising miller effect is usually less than falling one? \$\endgroup\$ – Roman Matveev Oct 18 '18 at 5:29
  • \$\begingroup\$ Vth indicates the point at which a conduction channel starts to form, so is quoted at a very low Id (maybe 100-500uA) , but the Miller effect will only come into play once the drain current is high enough to start bringing Vds down. There's typically about 1V difference between these two, and this the region you need to transition through fairly quickly to minimize switching losses. As for the on/off times, it's usually easier to discharge the gate than to bring it up, some gate drivers have an asymmetric sink/source rating that causes this - and sometimes the difference is intentional. \$\endgroup\$ – Phil G Oct 18 '18 at 13:56

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