We have designed hardware circuit which validates voltage regulator maximum output current. So we designed op-amp circuitry to control gate drive of the Power MOSFET and it will work in active region and pass the regulator output current through MOSFET. Here the Mosfet is our Load.

Issue: In our design we are capturing the output current wave form it shows the overshoot and undershoot in it. I suspect MOSFET input capacitance causing this issue. We have RC circuit for compensation to this but I need to understand this issue clearly and what are the possibilities causing the issue. Kindly help me on this

Attached is our op-amp circuit schematic and MOSFET design.enter image description here enter image description here

Sorry for delaying to upload the output wave form where I can see overshoot, undershoot in it (circled in yellow)

enter image description here

  • 3
    \$\begingroup\$ Surely the waveform itself and details about how you measure it and attach the probe is not important enough to mention it here. \$\endgroup\$
    – PlasmaHH
    Oct 18, 2018 at 8:04
  • \$\begingroup\$ The overshoot could be from the measurement, supply frequencies \$\endgroup\$
    – Voltage Spike
    Oct 18, 2018 at 18:40
  • 2
    \$\begingroup\$ It is not clear what out is, and what in is. 4 different nets that share names? \$\endgroup\$
    – Undertalk
    Oct 18, 2018 at 18:59
  • \$\begingroup\$ RAIL1_GD1 net is driving MOSFET gate voltage by op-amp in first circuit. RAIL1_IS1_H/_L net used to sense the load current in volts and given to error amplifier in first circuit back. \$\endgroup\$
    – ramesh6663
    Oct 22, 2018 at 8:53
  • \$\begingroup\$ DON’T PARALLEL MOSFETS WITHOUT INDIVIDUAL GATE RESISTORS! caps lock off Also, show layout and decoupling. Where are your pull-down resistors? \$\endgroup\$
    – winny
    Oct 22, 2018 at 9:11


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