Output filters for power supply design

I am trying to develop a design for a power supply. At the output of my design is a diode rectifier with a capacitive filter output. I've been told that I should expect to see an ESR of zero or something along those lines in my frequency response, but I'm not quite sure what that typically looks like or what that would look like in my frequency response.

Does the filter create a zero and how can I calculate the location of the zero? How would I know there is no additional poles added to my response as well? Is there some way I can simulate this to see what it looks like?

I can provide you a general schematic of the rectifier and output capacitor filter (this is the same as my design):

• Can you post a schematic of your power supply? – Chris Laplante Sep 12 '12 at 23:01
• I can provide you a general schematic of the rectifier and output capacitor filter here. (this is the same as my design) – suzu Sep 12 '12 at 23:51

Your output filter response should basically be the 20 dB/decade response of the capacitor.

The ESR zero will depend on the number and type of capacitors you're using. It's the natural corner frequency formed by the effective ESR and total capacitance:

$F_z = \dfrac{1}{2 \pi \times R_{esr} \times C_{out}}$

The gain slope will swing more positive at the zero, and you'll see the phase changing as well. You can easily use a free SPICE simulator like LTSpice IV to model the output precisely (with ESRs, ESLs, etc.) and generate a Bode plot.

• Hi, I'm curious to know what you mean by the ESR zero depends on the number of capacitors I am using? The way I derived it, it seemed that the location only depends on R_{esr} and C. Could you give me some more information on this? – suzu Sep 13 '12 at 7:00
• If you have a bunch of capacitors in parallel, the overall performance of the filter approaches that of a single capacitor with equivalent ESR and total capacitance (assuming the layout is well done.) – Adam Lawrence Sep 13 '12 at 12:44
• @Madmanguruman Just to clarify, you mean to say if there are 4 parallel caps, we can model this impedance as (with ESR) $$\frac{1+sCR}{4sC}$$ meaning that the output filter is providing a zero at 1/CR and a pole at 0Hz? Unfortunately, this method doesn't seem to be the same as what my data shows, so please let me know if I am calculating this with the wrong method. Thanks – suzu Sep 14 '12 at 0:39
• Modeling paralleled electrolytic caps will most likely result in a lumping together of the C values and paralleling of the ESR values. 4 caps in parallel give you 4 * C and ESR / 4. In real life they rarely balance out exactly due to stray resistances and inductances. Any ceramic caps on the rail can also dramatically reduce the ESR. – Adam Lawrence Sep 14 '12 at 1:11
• Incidentally, is this just a mains-frequency power supply with no feedback, or is the input high-frequency AC square waves? – Adam Lawrence Sep 14 '12 at 1:20