How to have an in-system check in an FPGA based system that it has been reset?

Question

I have a system based on Altera's MAX10 device that is doing the following tasks:

1. receives the data and stores it on an on-chip flash memory only once.
2. reads all the data from on-chip flash, stores it into a 2D register and relays it to another system at a certain frequency.

The first part (i.e. reads all the data from on-chip flash, stores it into a 2D register) of the 2nd task is performed only once, but if the system resets it again needs to read from the flash. Now how can I check if the system has been reset, and after reset whether it earlier saved any data in the memory or not. Further I don't want to perform a flash read operation to check whether the system has been reset or not and whether the data has been saved in the memory or not, because of its time cost. Would appreciate any ideas.

Answer 1

Important note: this is impossible to solve. As I mentioned in a comment: expecting internal state to be corrupted and adding more internal state to detect corruption invariably leads to a hornet's nest.

That being said, there's precedent to doing this: spaaaaace. Chips being sent into space require that any internal state can be corrupted in any way without it blocking the chip. Generally only single bit errors are required to be detected and repaired by ESA/NASA standards, but code will be written to detect as many of them as possible.

Solutions have to take into account two main corruptions:

One hot encoding for state machines with a safe state Encode all of your FSMs using a one hot encoding technique and start from a safe reset state that precedes your initial state. When you detect an impossible encoding, always revert to that reset state. Be aware that this does not mean you cannot use self-defined types for states in VHDL, proper use of when others => and your synthesis tools can do this for you.

Checksum your data Have an extra condition when writing data to the following system: the data you prepare to send checks out. If it doesn't, you reload. Since this checksum can be done on the fly in basically all modern FPGAs, you don't require extra state. CRC packages can be downloaded across the web (e.g. here)

These two solutions combined with a clean design catch all state that the system you describe should contain, if there's more, that's just bad design. Of course, power glitches won't even give you a guarantee that your bitstream survived on a MAX10.