I am designing the simplest form of a camera: an FPGA that interfaces an image sensor and sends the acquired data to the host device via USB 3.0. There is no processing on the FPGA, it is used for sensor control and data acquisition.
By studying various resources online, I observed that typically a DRAM is included in the design to store sequential frames as well as intermediate processing results. At first, my plan was to implement:
Image Sensor ==> FPGA ==> DRAM (Acquisition)
DRAM==>FPGA==>USB Controller (Transfer to host)
Since no image processing is done, I was wondering if it is safe to omit the DRAM in the design for reducing design complexity. So, the pixel data will go directly from the FPGA to the USB Controller in every cycle, and implementing a small internal RAM as a very small pixel buffer in case there is a temporary stall from the USB controller.
Is that feasible or I will have many frame losses due to transfer bottlenecks?