# Inverter Design - High Side MOSFET - Slow Switch Time

I've posted previously on a similar issue which can be found here

Overview:

My design is a 3 phase inverter with:

1. MOSFETS are STF10N60DM2
2. Gate Driver is 6EDL04N06PT

I'm using only a single high and low MOSFET for some testing.

The picture of my setup looks like:

The specifics of the setup are:

1. 30VDC Bus Voltage (But the design is to be used at 310V)
2. 10R Gate Resistors
4. Vth of the MOSFETS are 4V
5. VCC to the driver is 16V
6. The coloured circles match the probe points on the scope capture.

The Objective:

The object of the test is to check the switching response of the MOSFETS. During the testing I found that the High side MOSFET appears to switch off, in that Vgs < Vth however there is still voltage on the phase terminal (to the load). This voltage decays over some 3uS.

What I'm trying to determine:

1. When the lower MOSFET is switched on there is still a significant voltage at the phase connection, this is equal to DCBus and at 310V creates quite a disturbance.

2. Where is the stored energy coming from after the upper MOSFET is off. I don't have any additional capacitors, other than a small 100nF ceramic as the bootstrap caps and some filtering on the VCC.

The scope capture is shown below:

Specifics of the capture:

1. D0 and D1 are the PWM 1H/L digital inputs into the driver
2. Yellow = Lower gate (I have to pulse this for the bootstrap caps)
3. Purple is the Upper Gate
4. Blue is the Phase Voltage
5. White is the math Vgs (Delta between Purple and Blue)

My Questions:

1. Can anyone please describe why the phase voltage / gate voltage takes so long to decay? Obviously the load resistor plays a part in the decay, but where is the energy coming from that has to be bled by the resistor?

2. Is it possible that because the phase connection is linked directly to the gate driver's VS pin, that there is some magic within the gate driver preventing the phase voltage to drop? I doubt this is the cause as there is no direct connection from the gate driver to DCBus after the upper MOSFET is off.

3. Is the upper MOSFET actually switched off? Even though the Vgs is about zero, and by all accounts the MOSFET SHOULD be off, I'm wondering if it actually is not properly switched off..

• You can easily measure the time-constant of the delay. Measure out about 63% or so of the decay voltage and work out the time between those two levels. This provides $\tau=R\cdot C$. Since you know your R values, it's just a matter of figuring out the C value from that. You should be able to identify what is close to that value (gate capacitance, etc.) – jonk Oct 20 '18 at 4:43
• Can you find anything that is about $3\:\text{nF}$? For my money, take a look at the spec where it says that the total gate charge is about $15\:\text{nC}$ at a voltage of about $V_\text{GS}=10\:\text{V}$. That spells out about $1.5\:\text{nF}$ already, to me. And that's just the typical figure. – jonk Oct 20 '18 at 4:58