2
\$\begingroup\$

I've posted previously on a similar issue which can be found here

Overview:

My design is a 3 phase inverter with:

  1. MOSFETS are STF10N60DM2
  2. Gate Driver is 6EDL04N06PT

I'm using only a single high and low MOSFET for some testing.

The picture of my setup looks like: Test Setup

The specifics of the setup are:

  1. 30VDC Bus Voltage (But the design is to be used at 310V)
  2. 10R Gate Resistors
  3. 820R Load Resistor
  4. Vth of the MOSFETS are 4V
  5. VCC to the driver is 16V
  6. The coloured circles match the probe points on the scope capture.

The Objective:

The object of the test is to check the switching response of the MOSFETS. During the testing I found that the High side MOSFET appears to switch off, in that Vgs < Vth however there is still voltage on the phase terminal (to the load). This voltage decays over some 3uS.

What I'm trying to determine:

  1. When the lower MOSFET is switched on there is still a significant voltage at the phase connection, this is equal to DCBus and at 310V creates quite a disturbance.

  2. Where is the stored energy coming from after the upper MOSFET is off. I don't have any additional capacitors, other than a small 100nF ceramic as the bootstrap caps and some filtering on the VCC.

The scope capture is shown below: enter image description here

Specifics of the capture:

  1. D0 and D1 are the PWM 1H/L digital inputs into the driver
  2. Yellow = Lower gate (I have to pulse this for the bootstrap caps)
  3. Purple is the Upper Gate
  4. Blue is the Phase Voltage
  5. White is the math Vgs (Delta between Purple and Blue)

My Questions:

  1. Can anyone please describe why the phase voltage / gate voltage takes so long to decay? Obviously the load resistor plays a part in the decay, but where is the energy coming from that has to be bled by the resistor?

  2. Is it possible that because the phase connection is linked directly to the gate driver's VS pin, that there is some magic within the gate driver preventing the phase voltage to drop? I doubt this is the cause as there is no direct connection from the gate driver to DCBus after the upper MOSFET is off.

  3. Is the upper MOSFET actually switched off? Even though the Vgs is about zero, and by all accounts the MOSFET SHOULD be off, I'm wondering if it actually is not properly switched off..

Thanks in advance!

Update 2018-10-22:

I've struggled to find almost anything on the web about this issue (specifically the transients that occur during switching). However I did find an Infineon application note

The image from the app note is appended below, and clearly shows the same conditions that I've encountered on page 10. It also shows the switching transients that I'm experiencing.

Infineon App Note

\$\endgroup\$
  • 1
    \$\begingroup\$ You can easily measure the time-constant of the delay. Measure out about 63% or so of the decay voltage and work out the time between those two levels. This provides \$\tau=R\cdot C\$. Since you know your R values, it's just a matter of figuring out the C value from that. You should be able to identify what is close to that value (gate capacitance, etc.) \$\endgroup\$ – jonk Oct 20 '18 at 4:43
  • \$\begingroup\$ Thanks @jonk, its about 3nF. The high side gate driver actually switches off very quickly, but the longer decay is whats causing me issues. \$\endgroup\$ – SafetyLok Oct 20 '18 at 4:52
  • 1
    \$\begingroup\$ Can you find anything that is about \$3\:\text{nF}\$? For my money, take a look at the spec where it says that the total gate charge is about \$15\:\text{nC}\$ at a voltage of about \$V_\text{GS}=10\:\text{V}\$. That spells out about \$1.5\:\text{nF}\$ already, to me. And that's just the typical figure. \$\endgroup\$ – jonk Oct 20 '18 at 4:58
  • \$\begingroup\$ @jonk Assume it is 1.5nF and that it's across the upper FET, hence the discharge curve, how come it plays such a disturbing role in this system. My few days of googling have yielded very few people describing similar issues. \$\endgroup\$ – SafetyLok Oct 20 '18 at 5:16
  • \$\begingroup\$ Relatively high sink and source capability is often important for mosfet drivers operating at reasonable frequency rates. I can't speak to why you haven't googled up the issue. That said, anytime I see an RC decay curve I start looking for a dominant R and a C. All this means is that you have a passive system on at least one side of the process. I haven't looked at your device/schematic. But if you are getting good edges on the rise, but slow ones on the fall, this means active rise, passive fall. Probably needs to be addressed somehow. \$\endgroup\$ – jonk Oct 20 '18 at 7:57

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Browse other questions tagged or ask your own question.