I'm an electronics engineering student and want to develop a high voltage switch with normal Si N-MOSFETs. After some research, I discovered cascode switches for this application. Most of these cascodes use depletion SiC JFETs. But those are expensive, so I tried to develop a circuit with standard enhancement N-MOSFETs. I've chosen the STD3NK100Z (Datasheet), because of the high Vds, the low price and the availability in TO-220 (for the first prototype) and D-PAK (for SMD). Now I'm stuck at simulating the circuit in LT Spice XVII (64bit)...

I used the PSpice Model from here. Simple circuits with this model seem to work fine:

enter image description here

And produce the following output:

enter image description here

However, if I try to simulate more MOSFETs the simulation becomes really slow. My take on a cascode circuit is this:

MOSFET Cascode

But LT Spice says my timestep is too small.

It is also strange, that with another MOSFET (SIHP5N50D) model (from here) and the same schematic, LT Spice produces the following Output:

enter image description here

That is roughly what I'm trying to achieve. But the simulation only seems to work with V2 = 2kV. If I try higher values, Spice seems to calculate for infinity.

Changes in the .tran directive don't seem to help. I've tried playing with the Reltol, Abstol, Gmin, Chgtol and Trtol Spice parameters, but to no avail. Does anybody know a solution to this?

P.S. I'm new here, and hope I'm doing this right. If you need more pieces of information feel free to ask.

  • \$\begingroup\$ subcircuit models add a lot complexity, ltspice works best with models that are optimized for it, like their vdmos models. Also having high resistors like the 1G near a diode isn't going to speed things up. You could try increasing numdgt to a value high enough to force it to use doubles to decrease roonuding errors. also trying alternative solves sometimes helps. \$\endgroup\$
    – PlasmaHH
    Oct 22, 2018 at 13:29
  • \$\begingroup\$ Ok, thanks for the fast reply. I tried ".options numdgt=x", with different values for x ranging from 0.1 to 100. LTSpice Wiki says that the standard value for numdgt is 6. Changing it doesn't seem to solve the issue. What would be a value "high enough" for numdgt? Should I try to build a vdmos model from the datasheet? I've also tried different solving methods, but it doesn't seem to speed thing up. \$\endgroup\$ Oct 22, 2018 at 13:40
  • \$\begingroup\$ probably 15 or so? I have seen programs that are able to guide you to create a vdmos model but for most the datasheet info is not enough, you can give it a try though. How slow are things exactly? You could also try using a similar ltspice own part, iron out the worst things and then switch to your own. \$\endgroup\$
    – PlasmaHH
    Oct 22, 2018 at 13:45
  • \$\begingroup\$ Most of the time, the simulation just stops at around 50ns. It calculates some minutes, then displays the timestep is too small. I just changed the Reltol option to 10. Then the simulation runs, but the waveforms look kind of crazy. Am I right, that Reltol is the relative calculation error? \$\endgroup\$ Oct 22, 2018 at 13:52
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    \$\begingroup\$ Some (subcircuit) models like to include the terminal parasitics in the form of inductances, which cause excessive very high freq. ringing that cause the timestep to shrink to a stall. Open up the subcircuit and try to either comment out the first 3 lines (with the inductors) while taking care that the pins 1, 2, and 3 are directly connected to their series resistances, or add on the same lines Rpar=1m (dampens them while not disturbing the series resistances' values). Additionally, you could add .opt gshunt=<...>, default being 1g IIRC. If this is the cause, this is a known cure. \$\endgroup\$ Oct 23, 2018 at 7:29

1 Answer 1


[years later] I am playing around with a circuit much similar to yours, it seems quite prone to self-oscillation when the gate resistance is not set right. This also leads to extended calculation times.


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