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In an enhancement type MOSFET (an n channel one assumed here), when a positive gate to source voltage is applied, the holes of the substrate near the gate move deeper into the substrate away from the channel, and the electrons of the source and drain region accumulate near the gate to form the channel.

At the same time, the minority carriers of the substrate (electrons) should also be assisted by the electric field to accumulate in the channel region.

The book by Sedra and Smith mentions that only the source and drain electrons form the channel, while Boylestead's book states that the minority carriers of the substrate are involved in channel formation.

So, can I assume that both these mechanisms are involved in channel formation?

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  • \$\begingroup\$ Yes, both help form the induced channel but since the free electrons are readily available in the n+ region, they contribute a lot more. It would take a looong time for the channel to form if the process only relied on the minority carriers in the p-substrate. \$\endgroup\$ – Big6 Oct 23 '18 at 21:00
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Yes both mechanisms are involved. In my opinion Sedra and Smith is plain wrong if they claim that the channel only exists from electrons from source and drain.

That is because a MOS structure by itself (P-substrate - thin oxide - conductive polysilicon layer) so without drain/source regions, can already form a conductive channel at the edge of the P-substrate when a positive voltage is applied to the conductive layer (the gate). Like so:

enter image description here

When Vgb is large enough (more than Vt) a channel will form at the top of the (blue) p-type substrate. OK, it will not conduct anything to anything else but it will be there.

Perhaps in Sedra and Smith they refer to a channel of an active NMOS so where some drain current is flowing. Then indeed the electrons come from the source and travel through the channel to the drain.

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  • \$\begingroup\$ Right, so even when the drain voltage is 0 Volt, the gate voltage will cause the creation of a channel due to both mechanisms. Am I right with this statement? \$\endgroup\$ – Curiosity Oct 23 '18 at 21:00
  • \$\begingroup\$ This formation of "channels" is a problem for integrated circuits. Hence the "field implant", or the "channel stop" implant, is used everywhere on the IC's surface where no useful R/C/transistor has been laid out. This implant, from memory, is a highly doped layer, expected to require VERY HIGH VOLTAGES to invert. \$\endgroup\$ – analogsystemsrf Oct 24 '18 at 5:02
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    \$\begingroup\$ As usual a non-relevant and confusing (for OP) comment from analogsystemsrf. @Curiosity Yes, the drain voltage can be 0 volt and then there can still be a channel formed. See the picture I included: there is no drain yet still a channel can exist. \$\endgroup\$ – Bimpelrekkie Oct 24 '18 at 6:42

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