I created a simple 8-3 encoder module (called encoder8to3
) to replace a few repeated instances of Verilog code. I then tried to use the module in levers2.v
. I get the following error when I run a Verilog test file:
ERROR:HDLCompiler:69 - "C:/Documents and Settings/me/xilinx projects/wQCBG/levers2.v" Line 132: is not declared.
I see all sorts of examples of how to create modules, but not many on how to use the ones that are created. All I find are snippets of the use and not the declaration.
Will someone tell me how to properly declare encoder8to3
in levers2
please?
EDIT - codez, levers2, pared down.
module levers2(
input [7:0] LL,
input [7:0] RL,
output reg [10:0] DIVISOR,
output reg TD_ANY_MARK,
output reg TD_NUMBERS,
output reg TD_ONE_MARK,
output reg TD_DONT_DISENGAGE,
output reg FAULT
);
(snip)
reg [7:0] x;
always @(LL, RL) begin
(snip)
FAULT <= 0;
/*
encoder8to3(LL, x, FAULT);
(snip)
The encoder module itself is:
module encoder8to3(
input [7:0] A,
output reg [2:0] B,
output reg F
);
always @(A) begin
F <= 0;
if (A[0]) B <= 0;
else if (A[1]) B <= 1;
else if (A[2]) B <= 2;
else if (A[3]) B <= 3;
else if (A[4]) B <= 4;
else if (A[5]) B <= 5;
else if (A[6]) B <= 6;
else if (A[7]) B <= 7;
else F <= 1;
end
endmodule
I'm learning, and I'm just having some trouble with Verilog syntax. So somehow, I need to tell levers2 (the first piece of code) where to find encoder8to3
or perhaps, like c, just warn the compiler that the module will eventually be used.
encoder8to3
line - I'm at work now and can't check for sure. \$\endgroup\$ – Tony Ennis Sep 14 '12 at 14:08