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In Verilog, I can use an always block and make it trigger on a positive or negative edge.

Is it possible to trigger the block on both the positive and negative edge, and thus have it basically clocked at twice the rate?

If so, does it incur a resource penalty? Does the compiler need to duplicate the circuit, and generate one that triggers on the positive edge, and one that triggers on the negative?

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You can in simulation but the construct can not be synthesized.

For double edge clocking you need to build a circuit yourself from individual rising and falling edge FF's.

Does the compiler need to duplicate the circuit,

No, there is no (at last not yet) automatic conversion to hardware for a double edge clocked construct.


...So I could duplicate the construct manually, and have things running at double speed?

No, if it would be that easy everybody would do it.
The maximum operating frequency of a synchronous circuit is determined by the time it takes for a signal to leave a register, transfers through the logic and then still meet the set-up time of the next register.

If you use the rising and falling clock edge that time has just halved and the amount of logic you can use between registers also halves. The total circuit will not run faster.

Another a pitfall: it halves only if your clock has a perfect 50/50 duty cycle. Which is difficult to achieve so logic designers prefer to use one clock edge only.

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  • \$\begingroup\$ Thanks. So I could duplicate the construct manually, and have things running at double speed? \$\endgroup\$ – Rocketmagnet Oct 26 '18 at 9:29
  • \$\begingroup\$ It should be noted that while it isn't useful in most situations (ie, you could just double your clock rate instead), there are occasions where it is useful, mostly involving very small parts of a larger system that are simple enough to run twice as fast as the whole (and have enough work to do to justify it). Although even there, using a PLL to generate a double speed clock is probably simpler. \$\endgroup\$ – Jules Oct 26 '18 at 10:16
  • \$\begingroup\$ ok. So if my logic was simple enough, there's a chance that it might meet the timing requirements if double clocked? I have seen some Verilog code which calculates the 8b10b encoding in two stages using the rising and falling edges,. So that one symbol is encoded for every clock cycle. \$\endgroup\$ – Rocketmagnet Oct 26 '18 at 21:17
  • \$\begingroup\$ Yes, that can work. I normally 'fold' the logic of multiple loops. The place where I sometimes use rising & falling edge is for synchronizers to reduce the latency. But that also has a risk. \$\endgroup\$ – Oldfart Oct 27 '18 at 8:03

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