You can in simulation but the construct can not be synthesized.
For double edge clocking you need to build a circuit yourself from individual rising and falling edge FF's.
Does the compiler need to duplicate the circuit,
No, there is no (at last not yet) automatic conversion to hardware for a double edge clocked construct.
...So I could duplicate the construct manually, and have things running at double speed?
No, if it would be that easy everybody would do it.
The maximum operating frequency of a synchronous circuit is determined by the time it takes for a signal to leave a register, transfers through the logic and then still meet the set-up time of the next register.
If you use the rising and falling clock edge that time has just halved and the amount of logic you can use between registers also halves. The total circuit will not run faster.
Another a pitfall: it halves only if your clock has a perfect 50/50 duty cycle. Which is difficult to achieve so logic designers prefer to use one clock edge only.