I don't have familiarity with FPGAs and I haven't used VHDL for 21 years, so starting from scratch.

I am wondering if the following is possible/sensible.

  • FPGA running n "small" independent microcontroller cores, e.g. 8-bit AVR
  • each core has access to it's own CAN controller block
  • each core has access to two I/O signals
  • each core executes from external flash (divided up? shared? not sure...)
  • each core has it's own JTAG interface.
  • all cores share the same reset and clock inputs

I notice that on opencores.org there are some AVR implementations, but I am unsure how to work out how many I could squeeze onto a single FPGA.

The aim here is to create a compact setup for testing the same firmware running on many CAN nodes at the same time. Currently we connect together lots of off-the-shelf eval boards.


  • 4
    \$\begingroup\$ It is significant easier and cheaper to use dedicated CPU's. An FPGA which can contain multiple CPUs AND the program memories AND the data memories AND the CAN controller will be very big and expensive. I would just put a row of SOC with ARM cortex M3/M4 and CAN controller on a board. You can get them for about $2 each. \$\endgroup\$
    – Oldfart
    Oct 26, 2018 at 14:39

1 Answer 1


First of all: I suggest to use dedicated CPUs for this problem as Oldfart commented before. But to answer the question:

Two steps

  1. Get the estimated resource usage of one complex block. (the MCU plus CAN plus etc)
  2. Divide the available resources with the one block usage. Note that FPGA cannot be fit 100%. I suggest to keep the utilization <80%.

Get the estimated resource usage of one complex block:

A lot of core has estimated resource usage on one or more particular FPGA. Choose your FPGA and summarise the estimation.


Implement one block, synthesise and read the used resources.

Note that this will be just an estimation the final design can optimise some resources or run out because of timing problem.


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