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Hello Im making a register file 8x32 in verilog, the sim looks good but when I compile on quartus it makes

Error (10028): Can't resolve multiple constant drivers for net "rf[7][31]" at registerfile8x32.v(21) Error (10029): Constant driver at registerfile8x32.v(32) Error (10028): Can't resolve multiple constant drivers for net "rf[7][30]" at registerfile8x32.v(21) Error (10028): Can't resolve multiple constant drivers for net "rf[7][29]" at registerfile8x32.v(21) Error (10028): Can't resolve multiple constant drivers for net "rf[7][28]" at registerfile8x32.v(21) Error (10028): Can't resolve multiple constant drivers for net "rf[7][27]" at registerfile8x32.v(21) Error (10028): Can't resolve multiple constant drivers for net "rf[7][26]" at registerfile8x32.v(21) Error (10028): Can't resolve multiple constant drivers for net "rf[7][25]" at registerfile8x32.v(21) Error (10028): Can't resolve multiple constant drivers for net "rf[7][24]" at registerfile8x32.v(21) Error (10028): Can't resolve multiple constant drivers for net "rf[7][23]" at registerfile8x32.v(21) Error (10028): Can't resolve multiple constant drivers for net "rf[7][22]" at registerfile8x32.v(21) Error (10028): Can't resolve multiple constant drivers for net "rf[7][21]" at registerfile8x32.v(21) Error (10028): Can't resolve multiple constant drivers for net "rf[7][20]" at registerfile8x32.v(21) Error (10028): Can't resolve multiple constant drivers for net "rf[7][19]" at registerfile8x32.v(21) Error (10028): Can't resolve multiple constant drivers for net "rf[7][18]" at registerfile8x32.v(21) Error (10028): Can't resolve multiple constant drivers for net "rf[7][17]" at registerfile8x32.v(21) Error (10028): Can't resolve multiple constant drivers for net "rf[7][16]" at registerfile8x32.v(21) Error (10028): Can't resolve multiple constant drivers for net "rf[7][15]" at registerfile8x32.v(21) Error (10028): Can't resolve multiple constant drivers for net "rf[7][14]" at registerfile8x32.v(21) Error: Can't elaborate top-level user hierarchy Error: Quartus II Analysis & Synthesis was unsuccessful. 21 errors, 4 warnings Error: Peak virtual memory: 300 megabytes Error: Processing ended: Sat Oct 27 19:20:08 2018 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:01 Error: Quartus II Full Compilation was unsuccessful. 23 errors, 4 warnings

// Defino todos los parametros, entradas, salidas, regs,etc.
module registerfile8x32(addrsrc1_i,addrsrc2_i,addrdest_i,dest_i,
                        src1_o,src2_o,clk_i,rst_n_i,wr_i);

  input [2:0] addrsrc1_i;
  input [2:0] addrsrc2_i;
  input [2:0] addrdest_i;
  input [31:0] dest_i;
  input clk_i,rst_n_i,wr_i;

  output [31:0]src1_o;
  output [31:0]src2_o;

  reg [31:0] rf[7:0];
  reg [31:0]src1_o;
  reg [31:0]src2_o;
  integer i; //Necesito este iterador para el bucle for, con el que lleno todos los reg de 0s.

  // Esta parte de codigo es ASINCRONA, lo primero que miro es el reset, si esta a 0 reseteo todos
  // los registros.
  always@(negedge rst_n_i)
    begin
      if (rst_n_i == 0) // Miro si el reset esta a 0
        begin
          for(i=0; i<8; i=i+1) // Si lo está, lleno los registros de 0s.
          rf[i]<= 32'b0;
        end
    end

  // Positive edge clock y write enable.
  // Esta parte del codigo es nuestra parte SINCRONA, con el reloj y el write enable.
  always@(posedge clk_i or wr_i)
    begin
      if (wr_i) // Si write enable esta a 1
        begin
        rf[addrdest_i] <= dest_i; // Escribo en el registro de destino.
      end
      else if (!wr_i) // Si WE no esta activo, el registo mantiene el valor que ya tenia.
        begin
          rf[addrdest_i] <= rf[addrdest_i];
        end
    end
  // Esta parte del codigo vuelve a ser ASINCRONA mira las direcciones de lectura

  always@(addrsrc2_i or addrsrc1_i)
    begin
      src1_o <= rf[addrsrc1_i];
      src2_o <= rf[addrsrc2_i];
    end
  endmodule
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You can't make assignments to a signal (such as rf[]) in more than one always block.

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  • \$\begingroup\$ your are right! Now I have a new problem! hahahah \$\endgroup\$ – Gabe Logan Oct 27 '18 at 17:44
  • \$\begingroup\$ Error (10122): Verilog HDL Event Control error at registerfile8x32.v(21): mixed single- and double-edge expressions are not supported \$\endgroup\$ – Gabe Logan Oct 27 '18 at 17:44
  • \$\begingroup\$ as dave said, the error was having RF on 2 always structures, the last error I had is that signal rstn and clock cant be together with a double edge sensitive signal as WR \$\endgroup\$ – Gabe Logan Oct 27 '18 at 17:49
  • \$\begingroup\$ @Gabe your always block should look like always @(posedge clk_i or negedge rst_n_i) if (rst_n_i) begin /* async reset logic */ end else begin /* clock sync logic */ end. However, fpga have limited support for async reset; use sync reset instead (omit or negedge rst_n_i) \$\endgroup\$ – Greg Oct 27 '18 at 23:43
  • \$\begingroup\$ Oh greg I need an ASYNC reset, so the structure I have made is wrong I guess \$\endgroup\$ – Gabe Logan Oct 28 '18 at 14:45

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