Clock domain crossing issue can be solved by using asynchronus FIFO with input frequency f1 is of the source domain and f2 is of the destination frequency.

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If the data is sent in bursts, depth can be calculated by

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But what if the data is continuously sending ??

  • 2
    \$\begingroup\$ If f1>f2, no depth is sufficient ... Sooner or later you'll fill the fifo and start losing data. In all other cases, just use 2 flip-flops as described in this article: zipcpu.com/blog/2017/10/20/cdc.html \$\endgroup\$
    – Jules
    Oct 28, 2018 at 16:33
  • \$\begingroup\$ @Jules 2 flip-flop synchronizers only work for asynchronous data, i.e. you cannot use it to pass a parallel bus through a clock domain. If you want to pass parallel data, you need to use a more advanced techniques multicycle paths or asynchronous FIFOs. This article provides some very useful information about different types of clock domain crossings. \$\endgroup\$ Nov 25, 2019 at 5:09

1 Answer 1


The FIFO only works if the average input rate no greater than the average output rate.1

In this case, the output is continuous, so the average output rate is equal to the output clock rate.

If the input is bursty, then then average input rate is the input clock frequency multiplied by the burst duty cycle.

But if the input is continuous, then the average input rate is equal to the input clock rate, and this violates the first rule stated above. The FIFO will overflow.

1 Sometimes flow control is used to insure that this is true.


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