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This question is in reference to How to split Analog and Digital GND planes for a TQFN device.

For the PSoC3, the advice on how to separate the analog and digital ground is different depending on the package.

For the TQFP, it is suggested that the analog and digital grounds have separate ground planes.

layout

But for the TQFN package, it is recommended that the grounds are all connected to the same ground plane (the thermal pad).

GNDs connected to thermal pad

Why are these two recommendations different? (especially since Henry Ott recommends against it).

Does it really matter?

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  • \$\begingroup\$ Steven answered this in the answer that brought it up: "For parts with a thermal pad the split makes no sense, and you should connect the thermal pad to digital ground." The difference is that QFN has a thermal pad electrically tied to the chip substrate, but TQFP doesn't. \$\endgroup\$ – The Photon Sep 15 '12 at 16:38
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In general, datasheets give excellent advice that you ignore at your own peril. (Alas, like the advice of Cassandra, the advice in datasheets is often correct but misunderstood until it is too late).

However, even the writers of datasheets occasionally make mistakes.

The Burr-Brown application bulletin "Analog-to-Digital Converter Grounding Practices Affect System Performance" reports one experiment where a PCB was layed out both ways, and shows "a single ground plane" works best, even when it contradicts the "split grounds" advice given in a datasheet.

Splitting ground planes often seems to make an improvement. Making a single ground plane and fixing the actual source of the problem is even better. The Henry Ott article you linked and other "unsplit ground" articles at the MassMind explain why.

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Ideal is to have one ground plane and split the analog and digital components on either side of the meridian point. Henry showed this in your link.

Of course this is an internal layout design issue. Perhaps this is how it is done INSIDE the TQFP and then extended outside the chip. There may be a different layout inside the two chips with a large thermal ground plane of the TQFN inside and under the chip, (as others suggested), so we hope they have isolated the currents inside the layout to reduce common paths and the thick ground plane minimizes the voltage drop across the chip.

Aside notes Standard design practices for reducing conducted noise from the supply include the use of differential and common mode inductors from the input power connections and low ESR caps with RF caps in parallel.

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