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We are developing a board in which we would like not to use the analog features, like PLL, VCO and ADCs of a MAX10. UG-M10CLKPLL par. 2.3.6 states : "The only time that the VCO is completely disabled is when you do not have a PLL instantiated in your design". Does it mean that without instantiations of a PLL in the design we can assume that all the VCO are powered down or do we also need to connect to GND the VCCA pins? Unfortunately this last action does not accomplish what suggested in PCG-01018, which states "Connect these pins to a 3.0- or 3.3-V power supplies even if the PLL and ADC are not used" on Table 7.

Thank you

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  • \$\begingroup\$ As you pointed out documentation is clear on it - you must connect VCCA even if you do not use PLL and other analog stuff. I guess "disabled" means they are held in reset state and consume minimal power. \$\endgroup\$ – Anonymous Oct 31 '18 at 14:01
  • \$\begingroup\$ I would read it as saying all you have to do to power down the VCO is to not instantiate any PLLs. I guess you may have been confused by having "The only time" at the beginning of the sentence, which, strictly speaking, weakens the logical implication? \$\endgroup\$ – Justin Oct 31 '18 at 14:08
  • \$\begingroup\$ Justin, what I wondered was: "If I do not instantiate a PLL in the design, am I sure that the VCO will not oscillate?" Normally VCOs oscillate even if they do not have a voltage reference, therefore I thought that the only way to prevent their oscilation was to power them down. The simple "non-instantiation" of them to obtain this result will imply that they are NOT powered? \$\endgroup\$ – MRigh Oct 31 '18 at 14:59
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Does it mean that without instantiations of a PLL in the design we can assume that all the VCO are powered down

Correct. Or at least, it's powered down to the point of being "completely disabled".

or do we also need to connect to GND the VCCA pins?

No. As you've noted, these pins must always be connected to power. Grounding them is likely to damage or destroy the FPGA.

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