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  1. Will A and B always be the complement of one another regardless of what logic gates we use in the latch-like circuit? For instance (the two circuits shown as examples):

  2. How do we decide whether A and B will be the complement of one another or not?

  3. How to find the invalid states?

  4. Are these two latches?

schematic

simulate this circuit – Schematic created using CircuitLab

OR

schematic

simulate this circuit

I have tried following a few videos for instance this. But the presenter says that a certain state is invalid because Q and Q' should be the complement of each other. But how do we decide/prove that Q and Q' are the complement of one another?

UPDATE:

Truth Table of First Circuit:

enter image description here

How do I derive answers to the above questions from here.

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  • \$\begingroup\$ the video that you linked show you exactly how to prove which state is invalid in the first 5 minutes of the video ..... which part of the video was unclear to you? \$\endgroup\$
    – jsotola
    Oct 31, 2018 at 17:29
  • \$\begingroup\$ @jsotola He says (1,1) state is invalid because in that case both Q=0 and Q'=0. He did not mention why Q and Q' should be the complement of one another. \$\endgroup\$
    – Soumee
    Oct 31, 2018 at 17:38
  • \$\begingroup\$ no! not what he says! ..... what he does. ... do the same, draw a logic diagram for each of your circuits. .... please add the logic diagrams that you have produced to your question \$\endgroup\$
    – jsotola
    Oct 31, 2018 at 17:47
  • \$\begingroup\$ @Soumee, i just noticed that you are not the OP. ..... Q' means not Q, which is a complement of Q ...... you do not need to have a Q' as an output, but you will most likely need it internally \$\endgroup\$
    – jsotola
    Oct 31, 2018 at 17:55
  • \$\begingroup\$ @jsotola I have added the truth table.....Can you help me answer the above questions.... \$\endgroup\$
    – Anwesa Roy
    Nov 1, 2018 at 8:52

1 Answer 1

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To have a valid latch there must be three distinct values of the inputs:

  1. One set of input values that forces the latch to a logic 1 state

  2. One set of input values that forces the latch to a logic 0 state

  3. One set of input values that holds the current state, whether it is 0 or 1

A valid latch circuit must also have an output signal, typically called Q, that reflects the stored state of the latch.

Set up the truth tables for each circuit and see if you can find the necessary input conditions for the circuit to be a latch.

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  • \$\begingroup\$ If I draw the truth table, how will I watch out for the invalid states? \$\endgroup\$
    – Soumee
    Oct 31, 2018 at 17:44
  • \$\begingroup\$ How would I know which state is invalid? \$\endgroup\$
    – Soumee
    Oct 31, 2018 at 17:44
  • \$\begingroup\$ @Soumee, do not ask those questions until after you draw the truth table \$\endgroup\$
    – jsotola
    Oct 31, 2018 at 17:56
  • \$\begingroup\$ @jsotola Added....Please Check \$\endgroup\$
    – Anwesa Roy
    Oct 31, 2018 at 18:58
  • \$\begingroup\$ You added a truth table. Can you recognise a set of input values that statisfies Elliot's condition 3? \$\endgroup\$ Oct 31, 2018 at 21:51

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