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I am designing a simple, hobbyist single board computer similar to an Arduino using a Z80 CPU. The trouble I am running into is how the CPU addresses memory. I know that the Z80 uses pins A0-A15 to form an address bus, but reading "The Z80 Microcomputer Handbook", https://archive.org/details/The_Z80_microcomputer_handbook_William_Barden/page/n109, page 118 (In the book, not in the slider at the bottom of the webpage), second paragraph under "Interfacing ROM and RAM", it says that pin A15 is used to differentiate between the CPU addressing ROM or RAM. It says that when A15 is low, then ROM is being addressed, and when A15 is high, then RAM is being addressed. Is this true?

If it is, would I be correct in saying that that would take my 16 bit address bus to a 15 bit one, since one of those address pins is used to tell if the CPU is using ROM or RAM? Wouldn't it make more sense to AND MREQ and M1 together and connect that with the chip enable on the ROM, so as to make the ROM active whenever the Z80 is in opcode fetch mode?

The reason I ask this is because I would like the CPU to have 64K of ROM and RAM, if this is possible.

I'm new here, so any help is much appreciated, but if I did anything wrong, please tell me and I'll fix it.

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  • \$\begingroup\$ You only need to have a boot loader in static ROM. All the other software could be read e.g. from an I²C EEPROM. Such a loader routine can easily be implemented in less than 256 bytes. A SD card loader in less than 512 Bytes. So, use an OR gate on A9..A15 to create the ROM/RAM switch and enjoy almost 64K RAM. \$\endgroup\$ – Janka Oct 31 '18 at 19:10
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Look at the schematic on the following page. A15 is connected to the chip selects of the ROM and RAM to make that happen. It's not a function of the Z-80 per se -- it's a function of how the external memory is laid out.

Good choice -- the Z80 was the second microprocessor I ever worked with (in a TRS-80), and the first one I was paid to develop software on (at 13 -- you gotta love family businesses).

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Generally speaking, a bussed memory system requires an address decoder.

The project you are reading about appears to use a degenerate form of this, often called "partial address decoding" where one address line is used to differentiate between two memory devices. Each of the two possible states of A15 would address 32768 bytes of memory; if either or both of the memory devices connected to the respective halves are smaller than this (ie, use fewer than 14 connected address lines), then that memory will alias or repeat at multiple addresses within that range. Such a scheme is wasteful, but often justified for small systems which do not intended to have as much physical memory as the processor's address space could support.

Your goal of having 64K of ROM and also 64K or RAM will be problematic. Because the Z80 is a Von Neumann architecture machine, programs and data exist in the same address space, and there is no ready way to differentiate between them by hardware signals. In particular your idea of using the /MREQ signal is not workable, because this signal is used for both code and data memory access, and exists rather to differentiate all types of memory access from I/O access.

Typically, small systems including those based on the Z80 which want to install more physically memory than the processor can directly address must make use of bank switching. This is a fairly complicated to manage scheme whereby a latch somewhere in the I/O space is used to alter the behavior of the address decoder. For example, a ROM BIOS might be switched in to part of the address space overlying RAM, or perhaps a 4K or 8K chunk of the address space is used as a "window" into a larger area of memory, starting from a base address within that region which must be written to an I/O-mapped register.

If you are designing something from scratch, your desire to have this much memory should strongly point to using something other than a traditional Z80. 32 bit embedded processors (which can address 4 gigabytes!) are extremely inexpensive and power efficient these days. And there are some extended Z80 derivates that may give better native support for larger amounts of memory.

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    \$\begingroup\$ One popular option is the Hitachi HD64180, which has a Z80 CPU married to a simple MMU that maps memory in 4kB blocks, giving it the ability to address a total of 512kB or 1 MB of physical memory (depending on the chip package). \$\endgroup\$ – Dave Tweed Oct 31 '18 at 18:59
  • \$\begingroup\$ @Shades: You can do a lot of impressive stuff with just 64K of address space. I'd suggest that unless you have something to prove to to someone in 1980, that you go with 32K of ROM, at least 8K of RAM, and either leave the rest of the memory space fallow, or use it for block I/O. There's too many good cheap 32-bit machines out there to waste time screwing around with 64K memory spaces. \$\endgroup\$ – TimWescott Oct 31 '18 at 19:46

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