While reading the datasheet for the IS25LP512M series of Flash devices from ISSI I came across this weird command, 32h/38h called "QUAD INPUT PAGE PROGRAM OPERATION" (in section 8.11) with the following timing diagram:

32h/38h Diagram

This command seems very odd as it only uses the least significant bit of the data bus to transfer in the command and address, in contrast to all the other QSPI commands (as far as I can tell) like 02h, "Page Program Sequence In SPI Mode" which transfers the command and the address over all the data lines at the same time:

02h Diagram

It seems like it would a pain to implement this command on the Flash device and on the Master side.

Googling "32h flash memory" and looking through the results it seems like there are a number of other chips that implement this command, GD5F4GQ4UAYIG, S25FL-S, W25M321AV ect... So I assume it is from some kind of standard. (though it looks like the JEDIC Common Flash Memory Interface standard does not cover commands).

Where did this command come from? Who uses it? Why does it exist?

  • \$\begingroup\$ There is also the corresponding read command, 6Bh \$\endgroup\$ – asdfex Nov 1 '18 at 15:55
  • \$\begingroup\$ @asdfex good observation, I missed that! \$\endgroup\$ – Mark Omo Nov 1 '18 at 16:34

Those Flash ROMs can be operated in a number of ways: single, dual and quad data lines. The more lines you use, the faster is the reading or writing process for a larger amount of data. There are even more modes available, this specific device supports 27 (at least if I counted correctly) different read commands, all with their special number of address bytes, speeds and number of outputs.

Typically, the devices start up in the simplemost mode, which is single input/output and have to be configured to use any of the other modes. There are two ways how this can be accomplished:

First, the device can be switched to e.g. quad line mode, and then all subsequent commands and data are transmitted in parallel on four lines. Obviously, this is the fastest possible mode, but also requires a complex controller - it has to start in single line mode, configure the device to quad line (QPI mode) and then send commands on four lines.

This is the point where the commands 32h and 6bh come into play: Here all commands are transmitted as one line, and only data is transmitted on four lines. This allows for a simple controller: All commands are always sent on a single line and there is no need to switch modes. Data, on the other hand, is transmitted on all lines. This allows the device to reach almost the same speed as in QPI mode - the actual difference is small, as e.g. reading requires several dummy cycles until data is available.

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  • \$\begingroup\$ That was my thought as well, however everywhere I have seen you need to put the device in QSPI mode before you can use this command, from the datasheet: "Before the execution of Quad Input Page Program instruction, the QE bit in the Status Register must be set to “1” and the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction." Setting WREN in QSPI mode works as you would expect using all the data lines, and flipping the QE bit back to single wire SPI requires a standard quad command. \$\endgroup\$ – Mark Omo Nov 1 '18 at 16:34
  • \$\begingroup\$ @MarkOmo QE bit has to be set, but this is still different to issuing 35h, "Enable QPI mode" which is needed for the "real" 4-line operations. The QE bit is for additional safety because IO lines 2-4 do have another purposes in parallel or might even be tied to GND/VCC depending on the application. \$\endgroup\$ – asdfex Nov 1 '18 at 18:50
  • \$\begingroup\$ Ahh I see, thanks I don't know any situation where this would be simpler than full QSPI though, can you point to a device that depends on this mode to work? \$\endgroup\$ – Mark Omo Nov 1 '18 at 20:01

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