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I'm trying to put some logic gates together which would perform a task of finding out whether a number is zero or not. I came across a thread like this on here already (How to find out if a binary number is zero) and it says to "or every bit in the bus and then apply a not gate" but i'm not quite sure how this works.

I've tried drawing out the logic gates and their inputs/outputs, and what I've got is 4 OR gates which have inputs going from in[0] to in[7], so the first and second OR gates are:

Or(a=in[0], b=in[1], out=out0);
Or(a=in[2], b=in[3], out=out1);

And so on for the next two gates. I then get 4 outputs and i'm not entirely sure what to do with them now. I was thinking of somehow combining them into one input and then applying a single NOT gate to it, but i'm not sure if that would work, as well as applying 4 NOT gates to each of the outputs, but then i'd end up with 4 outputs after the NOT gate anyway, just inverted.

Anyone got any advice/tips on how I could do this?

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schematic

simulate this circuit – Schematic created using CircuitLab

Figure 1. The wordless answer.

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  • \$\begingroup\$ Thank you as well! Not entirely sure how I didn't see this \$\endgroup\$ – MajkelSine Nov 2 '18 at 13:41
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OR the first set of outputs together, then OR the results from that. Repeat until you have a single output. Pass that single output through a Not.

Or(a=in[0], b=in[1], out=out0);
Or(a=in[2], b=in[3], out=out1);
Or(a=in[4], b=in[5], out=out2);
Or(a=in[6], b=in[7], out=out3);
Or(a=out0, b=out1, out=out4);
Or(a=out2, b=out3, out=out5);
Or(a=out4, b=out5, out=out6);
Not(a=out6, out=out[0]);
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  • \$\begingroup\$ Oh my god I don't actually know how I didn't see this, thank you so much! I even tried doing the 4x OR initially, then putting their outputs into 2x AND, then from than AND into an OR and finally into a NOT. \$\endgroup\$ – MajkelSine Nov 2 '18 at 13:41
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There're a number of ways how to make the thing.

The main formula is

not(A OR B or C or D or ... or Z)

Then you build actual circuit diagram basing on the logic elements you have available.

not( (A or B) or (C or D) or ... or (Y or Z) )

for 2-input OR gates, or

not( (A or B or C) or (D or E or F) or ... or (X or Y or Z) )

for 3-input OR gates

not(A) and not(B) and not(C) ... and not (Z)

if you have a lot of NOT gates and one huge AND gate.

Thus as long as you identify what logic elements you have, then it will be possible to think about the most optimized circuit.

However if you build using VHDL or Verilog, you most probably not need to think about gates and optimizations at all - compiler will do the job for you. Your task will be to correctly spell the most readable logical equation (most probably, the first one on my list).

Important to note that if you build miltiple-stage logic circuit, the propagation delays of each stage (maximum of them at each stage) will sum up.

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  • \$\begingroup\$ An even easier way in an hdl is to use the "not equal to" operator, either != or /=. \$\endgroup\$ – Matt Nov 2 '18 at 13:48

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