# How to find out if the input of a logic gate is negative in two's complement?

I'm trying to create something which will output whether the input of the logic gate is a negative number or not in two's complement. I understand how twos complement works etc, but i'm not entirely sure how I would convert that into logic gates. I was perhaps thinking of using a Not gate at the start since there would only be one input and one output as well.

Thanks.

• "not in two's complement" two's complement is a definition, not a state. As such you can not detect if a signal is two's complement or not. (Assuming only ones and zeros). – Oldfart Nov 2 '18 at 14:49
• It's not clear what you're asking, since two's complement would be a number, or a collection of bits. And the most significant bit is the sign, meaning you already have the answer, without doing anything. – gbarry Nov 2 '18 at 14:51
• @Oldfart I think it's meant to be parsed as (whether the input is a negative number or not) (in two's complement). – Hearth Nov 2 '18 at 15:30

## 1 Answer

In two’s complement, the most significant bit (MSB) of all $$\ N \$$ bits involved is the sign indicator, so it would be sufficient to just look at the MSB of the bits going into your logic gate. Is it 0, then the number is positive. Is it 1, then the number is negative and you have to subtract $$\ 2^{(N-1)} \$$ from the number represented by the other $$\ N-1 \$$ bits in order to get the value.

A NOT gate's output of which the input is fed with the MSB will reflect the state of the input number. 0 means positive, 1 means negative.

• You should specify the "subtract 128" is for an 8 bit 2's complement number, or make it more generic and say subtract 2^(N-1), where N is the number of bits – ks0ze Nov 2 '18 at 16:51
• Yes you're right. Done. – joe electro Nov 2 '18 at 16:56
• How would I write this out in terms of logic gates? I'm gonna be writing it and then running it in a HDL, but i'm pretty sure I can't actually put any values when i'm writing it, and it's just stuff like Not(in=in, out=out); etc. – MajkelSine Nov 2 '18 at 18:44
• I don't know about HDL, but the gate to implement this is indeed a NOT gate, as I've edited into my answer. – joe electro Nov 2 '18 at 18:51
• Would it literally just be a single Not gate then? As the input for this should be 8bit, and the output should be 1 bit. I'd check but for some reason my virtual machine isn't working :/ – MajkelSine Nov 2 '18 at 19:05