Vivado : constraints setup for SPI interface with common clock

I have been using Vivado 2018 for a system level design and am having trouble with a SPI interface programming. A block diagram of my system is shown below.

The Artix-7 FPGA (on the motherboard) sends out a 3-wire SPI interface to 4 daughterboards. Following are the specifications :

FPGA :

• CLK : input clock to the FPGA
• SCLK : MMCM generated clock used to generate the SPI clock for the internal modules. These module generate the serial data to program the IC's on the daughterboard.
• SPI_SCLK : serial clock for the SPI interface common to all daughter-boards.
• SPI_CS : select lines common to all daughter-boards (using the select line from module #1 on the FPGA)
• SPI_SDI[1,2,3,4] : serial data specific to each daughter-board generated by the corresponding module on the daughter-board

Daughter-Board(s)

• CLK_BUF : a clock buffer for the SPI clock, which introduces a 5ns propagation delay.
• IC #1 --> IC #7 daisy chained on the daughterboard
• Common select lines to the daughterboards

CONDITIONS

• Delay on all SPI lines going from FPGA to daughter-boards are equal.
• delay introduced by BUF IC = 5ns
• tsetup (IC) = 5ns
• thold (IC) = 5ns

I have setup my constraint files as follows:

create_generated_clock -name sclk [get_pins clock_sources/inst/mmcm_adv_inst/CLKOUT2]

set_output_delay -clock sclk -max 5.000 [get_ports {spi_sdi[*]}]
set_output_delay -clock sclk -min -5.000 [get_ports {spi_sdi[*]}]

set_output_delay -clock sclk -max 5.000 [get_ports {spi_cs]
set_output_delay -clock sclk -min -5.000 [get_ports {spi_cs}]


QUESTIONS

1. Is this the correct approach to setup the constraint file for the SPI interface? Because of the propagation delay introduced by the CLK BUF IC on the daughter-board, I would like to delay the SPI_CS and SPI_SDI[1,2,34] lines by the amount equal to the propagation delay of the CLK BUF IC.
2. I believe the Modules 1,2,3,4 will have different net delays for the SPI_SDI[*] paths going out of the FPGA board. How should I ensure that these line see the same delay and hence are output synchronous to each other?
3. Similarly the SCLK going into each of the modules on the FPGA vs the SPI_SCLK going to the daughter-boards see different delay. Will this affect the serial data put on the bus?

I would like to understand how to tackle these issues. Any help is appreciated.

Thanks

First of all:

The timing (maybe) is the most essential and hardest part of the FPGA development. So first I suggest to read/watch timing guides.

Measuring technology:

Of course, it is impossible to make mathematically equal delays. (What's more not just delay, any two quantity cannot be exactly equal.) So you need to define the ranges in between you can tolerate the differences of delay. So more precisely what do you mean in synchronous?

Particular:

I suggest to read this guide. (This is an Altera guide, but the methodology, and the xdc syntax is the same.) There is a detailed template on page 9.

So you need to get the extremes of delays of your boards. The full pin-to-pin delays. Ask HW guys, or measure or simulate. You need the min-max values in all possible corner case. (Temperature, voltage production distribution etc.) Then fill the template with the values.

• Thanks for you inputs on this topic. I did follow the literature in the link you shared. I found a solution to my problem using constraints. If anyone is interested the link is here. link – CanisMajoris Nov 11 '18 at 20:18