How to get the MSB into a logic gate which will check if a number is negative or not?

Question

I need to create a logic gate which will find out whether a number is negative or not.

The input is 8 bits and the output is 1 bit, and if the input is 1 (i.e. negative number) then the output should also be 1, but if the input is 0, then the output should also be 0, so it kinda works like a NOT gate without the inverter.

I've read about the MSB and how it works and that I'd need to feed it in to the input but I'm not entirely sure how to write it. I'm going to be testing this on a HDL, so I'll need to write it a bit like:

Not(in=in[1], out=out[1];

and so on.

Any ideas?

Answer 1

In Verilog you'd just assign out = in[7] and be done.

There might be a gate available in your HDL that does this in one step. It might be named something like Buf or Buffer.

But if you don't have the documentation for your HDL, or there really is no way to simply tell it that one signal is an alias of another, you could cascade two inverters.

^{simulate this circuit – Schematic created using CircuitLab}

As an aside, the language you're using looks more like a netlist language than a full featured HDL. It's probably been designed solely to support your class, and isn't used in industry at all. Your professor or TA is probably the best one to explain the syntax and available gates to you.

Answer 2

You don't do anything. You can use the signal as is:

if (number[7]) // do whatever you want when it's negative else // do the positive thing

Or use an assign statement like suggested in comments.