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I need to create a logic gate which will find out whether a number is negative or not.

The input is 8 bits and the output is 1 bit, and if the input is 1 (i.e. negative number) then the output should also be 1, but if the input is 0, then the output should also be 0, so it kinda works like a NOT gate without the inverter.

I've read about the MSB and how it works and that I'd need to feed it in to the input but I'm not entirely sure how to write it. I'm going to be testing this on a HDL, so I'll need to write it a bit like:

Not(in=in[1], out=out[1];

and so on.

Any ideas?

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  • \$\begingroup\$ Can you explain what you mean by "testing this on a HDL"? Especially clarify whether you mean VHDL or Verilog, but also how exactly you plan to test it; in a simulator? On an actual FPGA? What simulator or FPGA? \$\endgroup\$ – Hearth Nov 4 '18 at 13:51
  • \$\begingroup\$ @Felthry i'm writing the actual chip in Visual Studio code. saving it as a .HDL file and then running it in a Hardware Simulator. I'm not exactly sure on the name/version as it's literally called Hardware Simulator \$\endgroup\$ – MichaelCerrera Nov 4 '18 at 13:58
  • \$\begingroup\$ Visual studio does HDL now? What device are you targeting when you compile it? \$\endgroup\$ – Hearth Nov 4 '18 at 13:59
  • \$\begingroup\$ @Felthry This is what i'm using. Turns out it's actually called Hardware Simulator 2.5, and the stuff on the left on the video is how my code for it looks like in VS Code. \$\endgroup\$ – MichaelCerrera Nov 4 '18 at 14:01
  • \$\begingroup\$ In Verilog you'd just assign signbit = in[7] and be done. If you have no other option you could cascade two inverters. \$\endgroup\$ – The Photon Nov 4 '18 at 15:18
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In Verilog you'd just assign out = in[7] and be done.

There might be a gate available in your HDL that does this in one step. It might be named something like Buf or Buffer.

But if you don't have the documentation for your HDL, or there really is no way to simply tell it that one signal is an alias of another, you could cascade two inverters.

schematic

simulate this circuit – Schematic created using CircuitLab

As an aside, the language you're using looks more like a netlist language than a full featured HDL. It's probably been designed solely to support your class, and isn't used in industry at all. Your professor or TA is probably the best one to explain the syntax and available gates to you.

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You don't do anything. You can use the signal as is:

if (number[7]) // do whatever you want when it's negative else // do the positive thing

Or use an assign statement like suggested in comments.

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  • \$\begingroup\$ So I've written it as Not(in=in[7], out=neg); but it doesn't seem to work. The language that i'm writing it in doesn't allow me to use if statements or whatever, all I can do is specify the chip name, the inputs and the outputs and that's it. \$\endgroup\$ – MichaelCerrera Nov 4 '18 at 15:47
  • \$\begingroup\$ What's the language? That's not vhdl or verilog, which are the only two mainstream hdls. I used some other fringe researchy ones in school though... \$\endgroup\$ – Matt Nov 4 '18 at 15:51
  • \$\begingroup\$ I honestly don't know, it's one that I use at school so it's probably the "fringe research ones" that you mentioned. It's layed out like the stuff on here \$\endgroup\$ – MichaelCerrera Nov 4 '18 at 15:56
  • \$\begingroup\$ Interesting. It looks like a custom hdl designed for teaching purposes. The only built in is NAND, and you use it to construct every other piece you need. You could certainly build a non-inverting buffer out of two cascaded buffers. But there also might be a way to use the wire directly since you don't need a buffer logically, they're generally used for physical design reasons, and you're modeling logic only. But unless you find people here with experience with this language you probably won't get a useful answer. Ask the instructor! \$\endgroup\$ – Matt Nov 4 '18 at 16:09

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