GPSDO control algorithm

Question

I am currently building my own GPS disciplined oscillator. I have a OCXO which is used as clock source for a microcontroller and one of its counters, and the 1PPS signal from the GPS module is connected to one of the capture inputs of the same counter.

Currently, I have following control algorithm: On the rising edge of the PPS signal, the counter's value is latched and compared to the previous value. If the difference is something else than 10000000, then the EFC voltage of the OCXO is increased or decreased accordingly. I have my GPSDO now running for several days, and it appears to be rock stable compared to a commercial GPSDO from Trimble, but it has the problem that it takes at least one full day until it properly locks. So I try to find a control algorithm which locks faster.

I was thinking whether I could implement something like a PLL in software.

E.g. each time the rising edge of the 1PPS signal occurs, I could calculate the value the timer should have the next time when the rising edge occurs and so on. By subtracting the actual timer value from the desired one, I get something like a phase error which I then could use to steer the OCXO. I would expect that this should lock faster than my current approach, and it should be more accurate because the integration time is basically infinite - even the smallest error will, at some point, lead to a phase difference greater than 1 count.

A further problem I have with both approaches is: how do I determine when the GPSDO is actually locked?

Are there other, probably better approaches for the control of an OCXO by a 1PPS pulse?

Answer 1

Your wish to use a software solution suggest that no hardware be added. That's a tough spec. So what hardware is offered within a common microcontroller that might be re-applied to resolve a time span under 100 nanoseconds?

An experiment was tried with Microchip's 16F1455 microcontroller. Its analog-to-digital converter is a successive approximation type with ten-bit resolution. The sampling window from the data sheet is not well-defined, but could be short enough to charge the internal sampling capacitor quickly. It might be quick enough to sample the 1pps pulse of the GPS output, and provide time resolution better than 100 ns.

The experiment clocked 16F1455 with a 10 MHz fixed crystal oscillator. The A-to-D was set to sample a function generator input square wave signal. Function generator frequency was set close to the sampling rate of the A-to-D converter, a period of 409.6 microseconds.
The function generator provides a five-volt peak-to-peak square wave with +2.5v DC offset, terminated with a 75 ohm resistor at the processor-end. Amplitude is set slightly less than 5v, so that “high” voltage yields a result slightly below the 1023 maximum count, and “low” voltage yields a result slightly above the zero count:
UART output allowed A-to-D samples to be collected by a PC.
Here is the sub-sampled output showing the function generator's square wave. Of interest is the square wave rise time and fall time. Rise time becomes a ramp-like rise, spanning about 4.5 samples. With an A-to-D resolution of one part in a thousand, time resolution of about one nanosecond is possible with this sampling technique.:

Improving time resolution from your 100 ns to 1ns should enable you to reduce phase-locked-loop settling time for the OCXCO. This is a kludge solution since the internal A-to-D sampler is not specified for this service. But it is one way to improve time resolution without extra hardware.