Trouble with simulating an SCR

Question

I was reading about SCRs and I'm trying to simulate 2N5060 SCR but having some issues when I plot the currents and voltages:

First by looking at the datasheet, I set the R4 to keep the gate current a bit less than 200uA.

For V2 I set the on time for the 5V gate pulse as 50u and 100us period.

I set a load which does not exceed 0.8A rated.

And here is the current through R1:

and here is the zoomed view:

And here is the plot of the voltage at the gate node:

Why is the load current has so many spikes?(it even gets worse with the shorter pulse ON times)

Is the gate voltage normal? It doesn't go to zero volt even I put a resistor between the gate and the cathode.

Why doesn't this SCR rectify the current? It passes the current both way, see my first plot.

I might be doing something fundamentally wrong but couldn't figure out the source of the issue.

edit:

The gate current:

Edit 2:

I increased the gate current as suggested and it still doesn't work.

And here is the SPICE model:

**********
*SYM=SCR
*SRC=2N5064;2N5064;SCRs;TECCOR; 200V 0.8A 
.SUBCKT 2N5064   1 2 3
*    TERMINALS:  A G K
QP  6 4 1  POUT OFF
QN  4 6 5  NOUT OFF
RF  6 4    400K
RR  1 4    267K
RGK 6 5    80
RG  2 6    9.09
RK  3 5    0.112
DF  6 4    ZF
DR  1 4    ZR
DGK 6 5    ZGK
.MODEL ZF   D (IS=3.2E-16 IBV=100U BV=200)
.MODEL ZR   D (IS=3.2E-16 IBV=100U BV=200)
.MODEL ZGK  D (IS=3.2E-16 IBV=100U BV=5)
.MODEL POUT PNP (IS=320F BF=1 CJE=402P TF=102U)
.MODEL NOUT NPN (IS=320F BF=100 RC=0.45 CJE=2.01N CJC=402P TF=3.74U)
.ENDS
**********

Answer 1

Below the trigger current, the SCR will act a bit like a transistor, so the gate current will be reflected in the anode current.

When the trigger current is reached, 200uA minimum in this case, the positive feedback takes over (given a sufficiently low load resistance) and the SCR latches on until the current drops below the holding current (stated as 5mA maximum for this part, but typically closer to the trigger current).

Edit: I don't have a working 2N5060 model,and I'm not going to import one, but here is the behavior with a 2N6564 which is similar. I've reduced the gate resistor and the load resistor. You can see the jaggies in the anode current near the zero crossings due to not reaching (or maintaining, on the falling edge) the minimum holding current.

The lack of triggering at low current may be a timing thing- the 200uA is okay for DC but not for 50usec pulses, or it could be a problem with the model, you can poke it and find that out.

Answer 2

You have wrongly interpreted the datasheet.

\$I_{GT}\$ Gate Trigger Current is the minimum current needed to trigger the SCR, not the max current it can handle.

\$I_{GM}\$ is the maximum gate current.

Hence your gate current need to larger than \$0.2\textrm{m}A\$

Also, add SCR spice mode.

I do not know why but this SCR start to trigger when Igt ≈ 10mA

Do you have in your LTspice the component named Scr_params?

If so use it instead and set these parameters

.subckt 2N5064  
    Scr params:
    + Vdrm=200v  Vrrm=200v    Ih=5ma       Vtm=1.7v     Itm=1.2
    + dVdt=30e6  Igt=0.2ma    Vgt=.8v      Ton=3.2u     Toff=30u
    + Idrm=10u