# How to generate a clock for my ring counter?

I want to run a 4 phase switched reluctance motor at low speed. The expected conduction sequence for the motor winding(y, r, b, g) follows the output similar to that of a 4-bit ring counter and thus I want to use a ring counter to give gate pulses to the power circuit of the motor.

The problem is with the clock. I want to be able to generate the clock from the outputs of two optical sensors in motors rotors. The following picture explains what exactly I want to achieve.

So, using the two sensor outputs, Q1 & Q2, I want to make a clock as shown in the clock waveform, which I will feed to my 4-bit ring counter to generate the 4 expected phase currents, Iy, Ir, Ib, Ig. (As can be seen, these expected phase currents follow the output of a 4-bit ring counter). Thus, will be able to run my motor at low speeds like 60/120/180 RPM.

How to generate the "clock" for the 4 bit Ring counter from the sensor outputs(Q1 & Q2) as shown in the figure above?

The clock will be positive edge triggered to the counter. Also, as the sensor output(effect) is generated as the motor rotates(cause) , initially I plan onto give a manual start to the motor via some extra circuitry and then as the motor attains some low speed, the external circuitry can be automatically disconnected and the counter circuit (using sensor outputs) will be used to run the motor.

Also, suggestions on some other different methods to run the motor are also welcome.

• Could you explain the logical connection between Q1, Q2 and CLK? I might be a bit unused to motor control, but I fail to see how clk can be derived from Q1, Q2. But I'm sure you have something reasonable in mind. Could you explain? – Marcus Müller Nov 4 '18 at 20:04
• Actually, there isn't any logical connection between the CLK and Q1 & Q2. – user58802 Nov 4 '18 at 20:24
• Then I don't understand your question "generate the "clk" … from the sensor outputs(Q1 & Q2) as shown … above". There has to be a logical connection, or your question makes no sense! – Marcus Müller Nov 4 '18 at 20:26
• And yes, you're right. Even, I think clk can't be derived from Q1 & Q2. However, I am more interested in how can I utilize Q1 and Q2 in some form of digital logic to generate continuously repeating pulses in the form of the four expected currents Iy, Ir, Ib and Ig as shown – user58802 Nov 4 '18 at 20:27
• You'll need to be more specific than that. You have some requirements for your clk in relation to Q1 & Q2 that for some reason you can't put into explicit words. Can you really at least try to do that? Like "Clk needs to have a rising edge whenever Q1 or Q2 has a rising edge, and no clk pulse might ever be longer than a Q1 pulse", or something. Just "some form of logic" would be: Ignore Q1 and Q2, and generate a square wave, and done. That's logic, and it fulfills all the requirements you have stated so far. So get better at stating the requirements! – Marcus Müller Nov 4 '18 at 20:31