Practically it is about 0.2 V when saturation starts. Why can't it go to 0?
Think about it - if you are forward biasing the base-emitter junction this means that the base is several hundred mV above the emitter for an NPN example. If you want the collector to be close to the emitter voltage (i.e. at 0 volts) then you are also starting to forward bias the base-collector region and, in-effect, the base keeps the collector potential from ever reaching 0 volts.
This is a simplified answer that suggests that the OP considers the NPN transistor as two back-to-back diodes for the sake of understanding how perfect saturation is impossible.
Considering an n-p-n BJT, we have Vbe = 0.7 V (approx). Saturation starts to take place when the forward current from the Collector-Base junction starts to cancel out the collector current due to the carrier flow from the Emitter-Base junction. This forward current starts getting significant from a forward bias of around 0.5-0.6 V on the collector-base junction (we already have a forward current for lower values of forward bias but they aren't significant "enough".. Termed as the soft saturation region). So at around initiation of saturation we can write Vbc=0.5 V or 0.6 V, giving Vce(sat) = Vbe - Vbc = 0.1 V or 0.2 V. From this point on, decreasing Vce raises the Vbc forward bias, pushing the device further into saturation (deep saturation)