# Setup and Hold Time: A general method to find whether a block satisfies the constraints

How to determine whether setup and hold time constrains are satisfied in a digital block? I encountered a question on the same, and it would be really helpful to know a general way to determine the same.

• Perform Worst-Case Analysis (WCA) for both. Analyze slack in the paths, data versus clock arrival. Search and explore "ASIC Static Timing Analysis" Nov 5, 2018 at 18:24
• How to find the clock period though in this case? Nov 5, 2018 at 18:36
• It might expect your answer to be in the form of LTE to a given frequency, and/or offset, for no violations(?) Maybe this example will help: vlsiuniverse.blogspot.com/2016/10/… you should be able to find several other examples too Nov 5, 2018 at 19:23
• Okay. Thanks. Can you please just tell me one additional thing: as per this logic, the frequency of the arrangement should be the inverse of (2+11+2+9+2) ns. Is it right? Nov 5, 2018 at 19:54
• yep... frequency, by definition, is 1/(time). Certainly you knew this already, given what you are working on(?) Timing "bites" even the most seasoned engineers, so be slow and deliberate in your calculations and draw it out if you need, each element on a separate line so you can see the delays and decide if it makes sense. Nov 5, 2018 at 19:58