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Assuming I set an external GPIO interrupt to highest priority, how many cycles does an STM32F0 MCU take to:

  • start executing the interrupt handler code
  • return from the interrupt

I expect that the answers will be ranges, but I might be wrong.

Will these two figures, plus the time my interrupt handler code takes to execute, equal the number of cycles "stolen" from the main loop?

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Look at the exception entry timing diagram on this page. Stacking

Entering the ISR on an Cortex M3 uses 12 clock cycles. For your ARM core and for leaving the ISR, maybe you can find a similar diagram.

The "stolen" cycles should equal all cycles used for entering, executing and leaving your ISR.

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  • \$\begingroup\$ It this in fact perfectly deterministic? Ie, that no contention for internal data paths or resources could extend this? What about if the ISR or vector table is located in RAM (or merely the required stack operations), and DMA is also trying to access RAM? It may be that it is deterministic, but it's something that needs to be considered when asking this about a modern architecture. \$\endgroup\$ – Chris Stratton Nov 6 '18 at 14:32
  • \$\begingroup\$ You are right. These are all parameters which can influence the timing. But I don't think you have designed a robust system if you have to go into such details. \$\endgroup\$ – A.R.C. Nov 6 '18 at 15:26

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