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I have a board without Reset input for my design. But I need to reset at fpga startup. Is there a verilog solution to generate this pulse ?

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  • \$\begingroup\$ What does the FPGA's data sheet say about resets? That's the first place you should look. \$\endgroup\$ – Chris Stratton Nov 6 '18 at 15:49
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The datasheet on MachXO says that

The MachXO registers in PFU and sysI/O can be configured to be SET or RESET. After power up and deviceconfigured, the device enters into user mode with these registers SET/RESET according to the configuration set- ting, allowing device entering to a known state for predictable system function.

Therefore, the simplest thing you can do is to configure all regs that need to be initialized with initial verilog construct or the equivalent understood by the tools.

If you still need a 'traditional' reset pulse, you can do it like this:

reg [3:0] rst_cnt;

wire rst_n = rst_cnt[3];

initial rst_cnt=4'd0;

always @(posedge clk)
if( !rst_n )
    rst_cnt <= rst_cnt + 4'd1;

This code again relies on the ability to set initial (power-on) values for the flipflops of MachXO.

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  • \$\begingroup\$ In fact, that does not work in fact : "WARNING - CG532 :[...] |Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored." \$\endgroup\$ – FabienM Nov 27 '18 at 9:35
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I finally found the solution thanks to lvd and tom-carpenter. Many FPGA can initialize there registers to 0 and nothing else. It's the case of machxo3.

Then doing that works for me:

reg [3:0] rst_cnt = 0;
wire rst_n = rst_cnt[3];

always @(posedge clk)
if( !rst_n )
    rst_cnt <= rst_cnt + 1;

Initial statement is ignored by lattice synthesis toolchain (even with synplify) if it's not a «force» or a memory initialization.

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