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I am currently designing a battery monitoring system for an 8 cell lithium battery pack. I originally made the device using a STM32 dev board and breadboard, with an SD card to log data. The system was accurate to +/- 0.01V, but had huge amounts of noise coupled into the ADC readings when there was read/write activity on the SD card.

My board is two layer due to cost constraints. I have managed to maintain pretty much a solid ground plane on the bottom layer. I identified the troublesome components (if not placed correctly) as the switching power supply, SD Card, USB and crystal oscillator. See schematic:

I think my main doubts at the moment are grounding of the board as well as signal integrity for my analog readings. Please could guidance be given on this.

SMPS - I am using a LMR23610 buck converter. I have followed the exact layout given in the datasheet. My only point of confusion was this in the datasheet:

Have a single point ground connection to the plane. The ground connections for the feedback and enable components should be routed to the ground plane. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior.

I think it means there should be a local ground plane on the top layer around the entire converter, which should only be connected to the PCB wide ground plane at one point (probably through a via). TI has made a sample board for this chip, except they did not follow this advice, rather they had 4 x vias next to each of the grounds of the input and output capacitors. I have done this where applicable for my design. Does my SMPS layout look ok, and is this the correct thing to do?

Power distribution - I wanted to disturb the bottom layer ground plane as less as possible, which caused quite a bit of difficulty in routing all the traces. In order to easily get the power traces connected I thought to just flood the whole top layer (apart from the SMPS region) with a polygon pour connected to 3.3V (buck converter output). I.e. There are two polygon pours in my top layer - A local GND for the SMPS and 3.3V output from the SMPS. Will this cause me any problems? I could have flooded it with GND instead, but I thought I could do all the GND connections with vias connected directly to my bottom layer.

My final doubt is how I have connected the crystal oscillator. I have created a ground island around the crystal and load capacitors with three vias connecting to the solid ground plane below. Would this be Ok? It is connected like this

enter image description here

Also for the digital signal lines (SD Card, USB), I have made sure to not disturb the ground plane below as I know the return currents will flow below the signal traces. All traces are 10mil width. I have followed all decoupling advice given by ST for this MCU.

Overall, is my layout Ok and there will not be any significant issues such as noisy readings on my ADC? I would readings of accuracy +/- 0.01V as I saw when I built this on a dev board. Any advice is appreciated as this is the second time I have made a PCB so I am a beginner.

Schematic: enter image description here enter image description here

Board: Top Layer

enter image description here

Top Layer Pour enter image description here

Bottom Layer enter image description here

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  • \$\begingroup\$ I would connect the GND vias directly to the bottom polygon without thermal reliefs unless you want high inductance and bad thermal properties on the heatsink of U14. You can set this up in the polygon connect style. Also the thermal reliefs in the GND connections of CN1 and C14 seem a bit thin. \$\endgroup\$ – Manu3l0us Nov 7 '18 at 8:20
  • \$\begingroup\$ The USB routing has not the correct impedance judging by the track width/space I can guess from your screenshot. You may also want some protection circuits on your inputs against ESD etc. Certainly, there would be much more to say, and if this is a commercial endeavor it may be worth to hire someone to make a product out of it. \$\endgroup\$ – Manu3l0us Nov 7 '18 at 8:24
  • \$\begingroup\$ Making sure that there is no active USB or FS data transfer, while doing conversion is easiest way to improve it, if you arent doing this already. \$\endgroup\$ – Rokta Nov 7 '18 at 8:26
  • \$\begingroup\$ Thanks for letting me know about the thermal reliefs. I will fix this up now. About the USB, I had checked in the STM32 datasheet and it said there is no need for inline resistors as the USB controller inside the MCU takes care of this. I found this to be the case with the dev board, which also did not have any inline resistors. About ESD protection - I asked this a while ago, see electronics.stackexchange.com/questions/398533/…. I was told that my resistors and OPAMPs will take care of this. What do you think? \$\endgroup\$ – Russell Nov 7 '18 at 8:34
  • \$\begingroup\$ @Russell The answer concerning ESD you got seems about right. If you don't have any special requirements you should be fine. If you are planning on certifying this as a product, you may want to check the applicable standards. Concerning USB: I meant the differential trace impedance, not inline components. Concerning your measurement accuracy: With the voltage divider on the inputs and your reference voltage, +/- 10mV is about +/- 1LSB of the STM32 ADC. Due to the fact that battery voltage changes relatively slowly, you could implement additional noise-filtering/oversampling in software. \$\endgroup\$ – Manu3l0us Nov 7 '18 at 8:43
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When it comes to noise, it would probably help to add a couple of 10uF ceramic capacitors in proximity of the opamps, as well as to the SD card. The SD Card will have quite fast transients during the R/W operations, which will transfer as noise along the 3V3. Additionally as you are measuring batteries, you can get rid of a lot of the noise in FW, as the changes in the values on the batteries are very slow.

EMC and ESD If I understand correctly, this is going to be a product, and therefore it should comply to local emission regulations. The first things that I notice, are that you have no ESD protection on the SD card or the USB; I suggest adding some low capacitance TVS protection diodes on both power and data lines.

The USB traces should be routed as 90 Ohm differential pairs; if you do this correctly, you will reduce the chance of reflections on these lines, and therefore conducted emissions. I suggest you download the excellent PCB Toolkit from saturnpcb.com, it is a great tool, which has one function that will calculate for you the track impedance. It is not as good as the Polar tools, but it is free, and gets you what you need.

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  • \$\begingroup\$ Thanks for your advice, should i add these 10uF caps to the VCC lines of the SD card and opamps? This is not going to be a consumer product. It is something one of that I am doing. I have already added protection on the USB (USB LC6 IC). I thought I would skip it on the SD card because most of time this won't be made contact with. Thank you for letting me know about that tool. I will ensure that the impedance are correct. \$\endgroup\$ – Russell Nov 7 '18 at 19:20
  • \$\begingroup\$ Yes, the capacitors must be as close as possible to the opamps and to the SD card connector. \$\endgroup\$ – Elmesito Nov 7 '18 at 19:25
  • \$\begingroup\$ I have just used this calculator online - eeweb.com/tools/edge-coupled-microstrip-impedance. For 2 layer board my inputs were T = 1 oz/ft^2, H1 = 1.6mm, W = 45mil , S = 6mil(minimum from pcb manfuacturer), Er assumed = 4.5. This gave me 87.9R diff impedance. But the trace width is so thick? I can't even connect a trace this thick to the MCU pins, so what would be the best thing to do here? \$\endgroup\$ – Russell Nov 7 '18 at 20:08
  • \$\begingroup\$ I would recommend using 47mils track, and 7 mils gap, as it will give you a 90 Ohm Z Diff. The fan out from the connector and into the MCU will have to be as wide you can get them, and then transition to the values mentioned above. This is common practice, and although it is not ideal, the impedance mismatch is only for a short stretch. If you are not stuck with that board thickness, most Chinese will allow you to choose 1mm thick board at no extra cost. With that board thickness, the track would be 30 mils and gap 7mils \$\endgroup\$ – Elmesito Nov 7 '18 at 20:44

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