I have a MOSFET in series with the output of my amplifier to switch the amplifier output to the downstream circuitry. The MOSFET parasitic capacitance is seen as a load capacitance by my amplifier, and hurts its stability. The gate is driven by a DC signal that switches the MOSFET on/off. The body is biased at a negative DC voltage. I am thinking to use a resistor in series with the gate and a resistor in series with the body to reduce the effect of the gate-drain, gate-source, body-drain, and body-source capacitance.


Are there any trade-offs to placing a resistor in series with the gate and the body?

I am aware that the switching speed of the MOSFET is dependent on the time constant of the series resistor and the gate capacitance.

Thanks for your help

  • \$\begingroup\$ I am more worried about the body diode of the mosfet you're adding in series to the output. Does your design account for this diode? \$\endgroup\$
    – Sven B
    Commented Nov 7, 2018 at 17:49
  • \$\begingroup\$ Yes, the substrate is biased to -5V to make sure the body diode is reverse biased. My amplifier rails are +/-5 so the drain/source will never be more negative than the substrate. \$\endgroup\$
    – DavidG25
    Commented Nov 7, 2018 at 17:59
  • \$\begingroup\$ If your using the mosfet as a current boost for the opamp in a negative feedback configuration, there are better ways to compensate the loop for stability than to worry about the gate. Also what is your desired bandwidth \$\endgroup\$
    – Voltage Spike
    Commented Nov 7, 2018 at 19:25
  • \$\begingroup\$ It is not a current boost. It is a switch in series with the output. The gate is driven by an MCU to control the switch. I am trying to get to around 200MHz. My spec is pulse width rather than bandwidth so my bandwidth figure is loose. \$\endgroup\$
    – DavidG25
    Commented Nov 7, 2018 at 19:28
  • 1
    \$\begingroup\$ Resistors in series with the body throws all sorts of latch-up alarms in my head, and isn't possible in all processes (we are talking IC design, right?) \$\endgroup\$
    – W5VO
    Commented Nov 9, 2018 at 0:05

2 Answers 2


The resistor on the gate would be fine, it will slow down your switching but that does not seem to be an issue for your design.

Regarding the body, if this was an IC I’d advise strongly against it, but being a discrete transistor I don’t see much of an issue. The body node will move with the drive signal but it will keep the proper bias.

However, you are not reducing the capacitances. What you are doing is introducing a zero in your response which should improve your phase margin. Inductors might also work.

But, at 200MHz you will have signal coupling through the FET. The way these switches are normally put together is with three devices in a T configuration with the middle connecting to ground. You should consider using a set of AC-coupled diodes as switches. Less parasitic to worry about.

  • \$\begingroup\$ Just curious, why would you advise against it for an IC? \$\endgroup\$
    – DavidG25
    Commented Nov 9, 2018 at 3:35
  • 1
    \$\begingroup\$ Because having a well with a voltage flailing around could cause the well-substrate junction to become forward biased, triggering a latch-up condition that could destroy the whole IC. It is done for some designs, but you have to be very careful on the layout of that well and the adjacent areas. \$\endgroup\$ Commented Nov 9, 2018 at 3:43
  • \$\begingroup\$ When do you have current to the substrate? Is it only AC current that is higher frequency than the corner frequency determined by Rdson and the parasitic capacitance between source-body and drain-body? \$\endgroup\$
    – DavidG25
    Commented Nov 9, 2018 at 19:02
  • \$\begingroup\$ @DavidG25 there are lots of parasitic components on an IC, none of which are documented in traditional models. Besides the capacitors and resistors, you have parasitic diodes, MOSFETs, BJTs, and SCRs. Any design has to take these into account, and process design and DRC rules strive to minimize their effect. Varying signals induce substrate currents via junction capacitances and metal-substrate capacitances, improper layout techniques could allow those currents to travel to a parasitic SCR gate triggering latchup. A floating well is very risky in this regard. \$\endgroup\$ Commented Nov 9, 2018 at 19:17

I'll address the gate resistor trade-offs.

As evident from a MOSFET model, there are two parasitic capacitances at the gate - Cgd, Cgs. Also, along with this you have parasitic inductance of the MOSFET leads and PCB tracks. So effectively, you have an LC circuit at the gate. This produces ringing at the gate terminal.

To damp this ringing (high frequency oscillation), a low value resistor - gate drive resistor is used. In short, the resistor beautifully damps the ringing but it comes with its own problems. I'll list out the pros and cons of gate drive resistor (high and low values)

Low Rg value

  • lower time constant hence faster switching
  • lower switching losses
  • less chances of parasitic turn-on
  • But, ineffective at damping the ringing at gate

High Rg Value

  • higher time constant hence slower switching
  • higher switching losses
  • higher chances of parasitic turn-on
  • but, extremely effective at damping the ringing at gate

Here's a nice video on gate resistor and its effects


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