I've just started taking a course in VLSI and from the little I know, this result seems a bit off. Below you can see the layout for the AND and NAND gate I designed :
They both seem to be working fine with rise and fall delays less than 0.5 ns. ( I will add the diagrams if necessary ) . Measuring dissipation at the output node of each gate while changing the capacitance of the node I get the following results :
I would expect the AND gate to have more dissipation but that is not the case here. I even checked the inverter's dissipation which reaches more than 2mWatts. Therefore, adding the inverter in series with the NAND gate should increase dissipation.
What am I missing?
Edit: The capacitance in the pictures is in femtofarads. The capacitance is added to the output of each gate, so it is added to the "out" node in the first picture ( AND gate ) and to the "out21" node in the second picture ( NAND gate ).
In both measurements the gates have the same exact inputs (clock pulses) and dissipation is measured at the output nodes. The AND gate has a rise delay of 700 ps and a fall delay of 330 ps.
Edit2: During the measurements I made sure that the two NAND gates are identical.