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I've just started taking a course in VLSI and from the little I know, this result seems a bit off. Below you can see the layout for the AND and NAND gate I designed :

enter image description here enter image description here

They both seem to be working fine with rise and fall delays less than 0.5 ns. ( I will add the diagrams if necessary ) . Measuring dissipation at the output node of each gate while changing the capacitance of the node I get the following results :

AND

enter image description here

NAND

enter image description here

I would expect the AND gate to have more dissipation but that is not the case here. I even checked the inverter's dissipation which reaches more than 2mWatts. Therefore, adding the inverter in series with the NAND gate should increase dissipation.

What am I missing?

Edit: The capacitance in the pictures is in femtofarads. The capacitance is added to the output of each gate, so it is added to the "out" node in the first picture ( AND gate ) and to the "out21" node in the second picture ( NAND gate ).
In both measurements the gates have the same exact inputs (clock pulses) and dissipation is measured at the output nodes. The AND gate has a rise delay of 700 ps and a fall delay of 330 ps.

Edit2: During the measurements I made sure that the two NAND gates are identical.

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    \$\begingroup\$ You are missing a lot of information. Which node exactly gets the added capacitance? What are the units of capacitance? How does the output rise/fall change between the two gates? How exactly is power measured? How are the inputs changed during the simulation, including their rise/fall times? \$\endgroup\$ – Elliot Alderson Nov 8 '18 at 12:48
  • \$\begingroup\$ @ElliotAlderson I tried to include everything you mentioned in my last edit. In case these are not enough I will upload a full picture of each gate's response soon. All the simulations and measurements are done by the software I use. \$\endgroup\$ – John Katsantas Nov 8 '18 at 14:59
  • \$\begingroup\$ Are the gate widths/lengths all the same? \$\endgroup\$ – Justin Nov 8 '18 at 15:08
  • \$\begingroup\$ I've pasted the same NAND gate in making the AND gate when taking the measurements. So yes, they are identical. Do I maybe need to measure dissipation at the input of the inverter? And then sum these values with those at the output? The sum is indeed bigger and it makes more sense. \$\endgroup\$ – John Katsantas Nov 8 '18 at 15:16
  • \$\begingroup\$ Are you trying to measure the current used by these gates? You should be measuring the current from the VDD supply, but you mentioned "dissipation is measured at the output nodes". Am I missing something? \$\endgroup\$ – Justin Nov 8 '18 at 15:48
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I like schematics so you're comparing:

schematic

simulate this circuit – Schematic created using CircuitLab

And you expect that the left circuit with NAND1 would consume less power than the right NAND2 + INV circuit.

If you assume that the complexity of the circuit is the only factor in determining the power consumption then you would likely be correct.

But more is / could be happening!

  • The power dissipation is related to charging the capacitor. In the NAND1 circuit there are 2 PMOS in parallel that can charge the capacitor.

    In the NAND2 + INV circuit it is the single PMOS in the inverter charging the capacitor.

    When those 2 PMOS in NAND1 are both switched on, the capacitor is charged more quickly but that could require a bit more power.

  • Are the Width and length of all PMOS the same? To me it looks like they might be different, that can also affect how fast the capacitor is charged.

If you really need to know what is going on then this is best understood when using an Analog circuit simulator like LTSpice. That might be taking this too far though.

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  • \$\begingroup\$ I uploaded the wrong picture for the NAND gate I used in the measurements. The NANDs I used (NAND1 and NAND2) for the measurements are identical. Sorry for that. Also, I think I'm measuring the dissipation only at the output of the inverter. Do I have to add the dissipation at the output of NAND2 to get my total losses? \$\endgroup\$ – John Katsantas Nov 8 '18 at 15:24
  • \$\begingroup\$ Do I have to add the dissipation at the output of NAND2 to get my total losses? For a fair total, yes you should. But since the output of NAND2 is only loaded by the inverter, its contribution will be small. So for the high value load capacitor, there will be little difference between the circuits as the load on the output will dominate. \$\endgroup\$ – Bimpelrekkie Nov 8 '18 at 15:30
  • \$\begingroup\$ Should "When those 2 PMOS in NAND2 are both switched on" be "_...NAND1..."? \$\endgroup\$ – TripeHound Nov 8 '18 at 15:36
  • \$\begingroup\$ @TripeHound Well spotted ! I'll correct that. \$\endgroup\$ – Bimpelrekkie Nov 8 '18 at 16:30

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