Why does my AND cmos gate have less dissipation than my NAND gate?

Question

I've just started taking a course in VLSI and from the little I know, this result seems a bit off. Below you can see the layout for the AND and NAND gate I designed :

They both seem to be working fine with rise and fall delays less than 0.5 ns. ( I will add the diagrams if necessary ) . Measuring dissipation at the output node of each gate while changing the capacitance of the node I get the following results :

AND

NAND

I would expect the AND gate to have more dissipation but that is not the case here. I even checked the inverter's dissipation which reaches more than 2mWatts. Therefore, adding the inverter in series with the NAND gate should increase dissipation.

What am I missing?

Edit: The capacitance in the pictures is in femtofarads. The capacitance is added to the output of each gate, so it is added to the "out" node in the first picture ( AND gate ) and to the "out21" node in the second picture ( NAND gate ).
In both measurements the gates have the same exact inputs (clock pulses) and dissipation is measured at the output nodes. The AND gate has a rise delay of 700 ps and a fall delay of 330 ps.

Edit2: During the measurements I made sure that the two NAND gates are identical.

Answer 1

I like schematics so you're comparing:

^{simulate this circuit – Schematic created using CircuitLab}

And you expect that the left circuit with NAND1 would consume less power than the right NAND2 + INV circuit.

If you assume that the complexity of the circuit is the only factor in determining the power consumption then you would likely be correct.

But more is / could be happening!

• The power dissipation is related to charging the capacitor. In the NAND1 circuit there are 2 PMOS in parallel that can charge the capacitor.

  In the NAND2 + INV circuit it is the single PMOS in the inverter charging the capacitor.

  When those 2 PMOS in NAND1 are both switched on, the capacitor is charged more quickly but that could require a bit more power.

• Are the Width and length of all PMOS the same? To me it looks like they might be different, that can also affect how fast the capacitor is charged.

If you really need to know what is going on then this is best understood when using an Analog circuit simulator like LTSpice. That might be taking this too far though.