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I am trying to create an 8-bit programmable up/down counter using D Flip flops. So far, this is what I have:

up/down synchronous counter D ff

The first 3 flip flops function correctly for both up and down, but the 4th doesn't. I was stuck on this problem for the past week and I couldn't find anything which helps.

Also, is there an easier way to solve this problem, perhaps without muliplexers?

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  • \$\begingroup\$ Hint what do you think the logic equation for the input to the xor for the fourth stage should be? \$\endgroup\$ – RoyC Nov 8 '18 at 18:32
  • \$\begingroup\$ @RoyC I have disconnected the wire from Q1 to the top AND gate right before the final multiplexer. I assume that the equation for the 4th flip flop would be similar to the 2 previous flip flops, and I believe I have reflected this in Logisim. Where is the problem? \$\endgroup\$ – erykkk Nov 8 '18 at 18:55
  • \$\begingroup\$ You are not giving us any clues as to how much you know about this sort of design. Try editing your question to add what you have tried to fix the problem and some details about what is going wrong. There are many articles out there about the design of synchronous counters. The fourth stage is going wrong, if you are following an article or tutorial you need to look closer at how the and gates feeding the fourth stage are wired. \$\endgroup\$ – RoyC Nov 9 '18 at 10:34
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After further research:

enter image description here

Arithmetic units and MUX all set to bit-width of 8.

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