# Inherent DC Bias in ADC sampling

I was just simulating the quantization behavior of ADCs of different bits, on data sampled by a 24-bit ADC. What I noticed that as we go towards ADCs with less bits a DC bias in the signal becomes more and more evident, with maximum value at 1 bit-ADC. The reason for this is, acc. to what I think, is that there are different number of digital codes representing positive and negative analog voltage values, for example in case of 8-bit ADC, we have 1-127(127 digital codes) for positive, 0 for 0 voltage, and -1 to -128(128 digital codes) for negative values, so negative voltages have one more digital code for them. and this effect becomes very clear with 1 bit ADC, where we have only digital codes of 0 and -1, so the sampled signal will always have negative bias, Please see the video below where I do the simulation and you can clearly see the signal moving downwards as I decrease the number of bits, The ADC voltage range is +50 to -50 units. So at 1-bit, I only have 0 and -50 samples and a clear negative DC offset.

So my question, how much of an issue is this ? I can simply remove the DC offset by using a high pass filter in Digital domain, are there any other concerns and ways in which my signal is affected ? Is this a very common issue and what else can I do to remove this DC offset ? Are there ADCs which have equal number of digital codes for positive and negative voltages ? What are they called ?

They don't have an inherent offset...they simply have a range which is asymmetrical around zero. Zero doesn't mean zero volts; what physical quantity each value refers to is a result of the hardware design. The observation here isn't that ADCs have inherent offsets, or in fact anything about ADCs; the observation is that, if you choose two's complement representation, you have an even number of possible values for any number of bits; if one of those values is zero, you have an odd number of possible values remaining, and can't distribute them equally among positive and negative.

Sign-magnitude representation solves this, but introduces other special handling, and all you've really accomplished is you lost one potential output value.

It would be good for you to look at some data sheets. This question will be answered, and a whole bunch of ones that you haven't thought of yet.

In general, even a 12-bit ADC has several counts of DC offset; a typical 16-bit SAR ADC may have 20 to 50. And that offset changes with temperature. Moreover, the inherent nonlinearity is usually more than that, as well.

If you could find an ADC with insignificant non-linearity and offset, all you'd have to do is calibrate out the offset.

• Looking at the LTC2380-24 (which I have used), it has a zero scale error of up to 10ppm (but with +/-8.388 million codes, that can still be quite a few counts). A note on this is that really high precision parts cost more :) Nov 9, 2018 at 9:52

Are there ADCs which have equal number of digital codes for positive and negative voltages ?

All of them are like this if you choose to use them that way and ignore the extra LSb of information that you get on the positive or negative side.

What are they called ?

Choose any you want and just digitally ignore the extra LSb. If you decide not to ignore the extra LSb then regard it as a bonus.

So my question, how much of an issue is this ?

It does appear to be an issue to you because you made a video about it. To most other folk it's a non-event I suspect.