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I'm trying to implement an 8-input AND gate using CMOS technology with the best number of stages and least delay (I have attached the schematic in the link given).

Using logical effort I have so far figured out that I should try to create a 5 or 6 stage design. I'm not sure how to find out the different configurations for a stage.

Can you give me some hint or source from where I learn more about how to find the different design configurations?

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  • \$\begingroup\$ "..gate with the best number of stages an..", what makes one number better than another number of stages? - Your... "schematic" doesn't tell me much, if anything at all, but it shows that at least you've been thinking about something which is good, I guess. - Have you thought about using a NAND followed by an inverter? Or are you exploring all possibilities, as your schematic seems to promote? \$\endgroup\$ – Harry Svensson Nov 9 '18 at 7:52
  • \$\begingroup\$ Also, how did you get to 5 or 6 stages? \$\endgroup\$ – Sven B Nov 9 '18 at 9:14
  • \$\begingroup\$ What is the meaning of the inverter on the first input? \$\endgroup\$ – betontalpfa Nov 9 '18 at 9:35
  • \$\begingroup\$ My impression is that digital electronic circuits are new to you. At the same time you are asking for "least delay" which in case of a 4-input AND gate is in the order of 30 nano seconds at 4.5 V (Yes, I looked that up in a datasheet). What system are you making that a few nano seconds delay is essential? Sorry if this sound impolite but do you know what you are doing? \$\endgroup\$ – Oldfart Nov 9 '18 at 10:53
  • \$\begingroup\$ @Oldfart yes indeed, im new to digital electronic circuits and its true I was a bit confused on what I was doing but now I have some idea. \$\endgroup\$ – steve norah Nov 11 '18 at 7:18
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I won't give a complete answer, since I assume this is homework, plus I don't really know the answer :). It's been a while since I've studied this, so I don't remember all of the terminology either.

The load of 4000 in logical-effort units is pretty large. You could make an 8-input AND gate using a tree of 2-input NAND gates with a depth of 3 followed by an inverter. That would be 4 stages, which you have already determined is not optimal to drive such a high load.

My suggestion is to do the NAND operation at the beginning and follow it with enough inverters to get to the desired strength, since inverters are simpler and have less of a scaling factor for logical effort

What I'm not sure about is whether it is more efficient to implement the NAND as a tree of 2-input NAND gates or just as an 8-input gate directly. In real life it's hard to implement an 8-input gate directly because you don't usually have enough supply voltage, but maybe that's not considered for this academic problem. Wikipedia states that the logical effort for an 8-input NAND gate is \$\dfrac{n+2}{3} = \dfrac{10}{3}\$, and I suppose that's a single stage.

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  • \$\begingroup\$ Thank you Justin, your comment helped me a lot in finding the number of stages. Im now working with the NAND2 according to your suggestion but ran intro some trouble I have updated my question. \$\endgroup\$ – steve norah Nov 11 '18 at 7:15
  • \$\begingroup\$ Sorry I'm not able to help more (don't have much experience beyond a month in a vlsi course of my own 10 years ago.) It looks like you're on the right track. You might need to try many different topologies to find the best. Writing a script could prove very useful. \$\endgroup\$ – Justin Nov 11 '18 at 13:35
  • \$\begingroup\$ About your simulation question. I usually sized the pmos large enough that the rise and fall delays were close. You could just put 4000 unit inverters on the output (don't actually place that many; if you set the instance name to end in [3999:0], it means that there are 4000 in parallel). Divide the delay by the delay of a separately simulated unit inverter (I don't remember what load it needs to simulate the unit delay). A unit inverter isn't a min size inverter; it should also have the same pmos to nmos ratio for equal rise/fall times \$\endgroup\$ – Justin Nov 11 '18 at 13:44
  • \$\begingroup\$ that should be angle brackets in the instance name actually, <3999:0> \$\endgroup\$ – Justin Nov 11 '18 at 13:53

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