# Implement an 8 input AND gate with least delay

I'm trying to implement an 8-input AND gate using CMOS technology with the best number of stages and least delay (I have attached the schematic in the link given).

Using logical effort I have so far figured out that I should try to create a 5 or 6 stage design. I'm not sure how to find out the different configurations for a stage.

Can you give me some hint or source from where I learn more about how to find the different design configurations?

• "..gate with the best number of stages an..", what makes one number better than another number of stages? - Your... "schematic" doesn't tell me much, if anything at all, but it shows that at least you've been thinking about something which is good, I guess. - Have you thought about using a NAND followed by an inverter? Or are you exploring all possibilities, as your schematic seems to promote? – Harry Svensson Nov 9 '18 at 7:52
• Also, how did you get to 5 or 6 stages? – Sven B Nov 9 '18 at 9:14
• What is the meaning of the inverter on the first input? – betontalpfa Nov 9 '18 at 9:35
• My impression is that digital electronic circuits are new to you. At the same time you are asking for "least delay" which in case of a 4-input AND gate is in the order of 30 nano seconds at 4.5 V (Yes, I looked that up in a datasheet). What system are you making that a few nano seconds delay is essential? Sorry if this sound impolite but do you know what you are doing? – Oldfart Nov 9 '18 at 10:53
• @Oldfart yes indeed, im new to digital electronic circuits and its true I was a bit confused on what I was doing but now I have some idea. – steve norah Nov 11 '18 at 7:18

What I'm not sure about is whether it is more efficient to implement the NAND as a tree of 2-input NAND gates or just as an 8-input gate directly. In real life it's hard to implement an 8-input gate directly because you don't usually have enough supply voltage, but maybe that's not considered for this academic problem. Wikipedia states that the logical effort for an 8-input NAND gate is $$\\dfrac{n+2}{3} = \dfrac{10}{3}\$$, and I suppose that's a single stage.