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I have to pilot a CMOS input 5 V chip device with a 7474 flip-flop with the lowest possible delay to minimize clock jitter. The signal is about 11.3 Mhz.

I have two options:

  1. 74HC74 (CMOS compatible) with a maximum speed of about 30 MHz

  2. 74AS74 with a pull-up resistor with a theoretical maximum speed of about 100 MHz

I would use the 74AS74 because this should have one third of propagation delay vs the 74HC74 (hence one third of clock jitter probability, I suppose), but I would need a pull-up resistor to reach CMOS input voltage levels.

I was thinking of about 1 kΩ of pull-up from the 74AS TTL output to the positive 5 V rail, giving a safe 5 mA load.

Questions:

  1. Which is the lowest safer pull-up resistor for a 74AS piloting a CMOS device? Websites recommends from 10 kΩ to 2.2 kΩ from TTL to CMOS. I would use 1 kΩ. Is it 470 Ω still safe and better?

  2. The 74HC74 runs at 30 Mhz, the 74AS74 runs at 100 Mhz. But which is the maximum speed (or propagation delay) of a 74AS74 with a pull-up resistor? Does the pull-up resistor jeopardise the 74AS' speed advantages vs the 74HC?

  3. To minimise jitter driving a CMOS: is it correct that any 74AS with a pull-up resistor is better than any 74HC device?

PS: don't want to use 74AC or other logic families. Question is only about 74AS vs 74HC.

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    \$\begingroup\$ Propagation delay doesn't equate to jitter - rise and fall times being poor equate to bad jitter performance. "Piloting"? Do you mean "inputting"? Adding a resistor doesn't usually affect prop delays. \$\endgroup\$
    – Andy aka
    Commented Nov 9, 2018 at 18:53
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    \$\begingroup\$ I see you worry a lot, but have you tried hooking up a 74AS74 to a CMOS logic gate to see its performance? You can evaluate the rise/fall time and observe if jitter exists through your oscilloscope with various resistor options you have in mind. I think you will get the answer by experimenting faster than getting an answer here. \$\endgroup\$
    – kaosad
    Commented Feb 6 at 2:03

3 Answers 3

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To minimize jitter, you have two concerns:

1) deterministic jitter, from Ground trash, electric and magnetic-coupled trash, and VDD trash.

2) internal on-silicon random-thermal-noise of that pullup resistor at the BASE of the multiple-emitter input transistors.

To address (1), its your task to USE GROUND PLANES, keep switching regulators far way (because of high dV/dT causing serious EFI, and high dI/dT causing serious HFI), and to implement "local battery" local-charge-provision VDD filtering (cascades of RC + RC low pass filter (1 ohm and 0.1uF, above a GND plane; two such LPF in series).

To address (2), you need to bring up the external node voltages quickly.

I'd operate the 74S on 5.5 volts. That speeds up the output.

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1) which is the lowest safer pull-up resistor for a 74AS piloting a CMOS device? Websites recommends from 10K to 2.2K from TTL to CMOS. I would use 1Kohm. Is it 470ohm still safe and better?

Check the datasheet of the device, there is a maximum output current for ViL (when the device is high ViH will pull little addtional current through the pull up). You should not exceed the IoL recommendation, for a SN74AS30, IoL is 20mA. That means at 5V you could go as low as 250Ω, it would probably be wise to not go quite that low and burn up lots of power, but maybe 1k. Since CMOS draws nA's of current the input stage for CMOS is negligible.

2) 74HC74 run at 30Mhz, 74AS74 run at 100Mhz. But which is the maximum speed (or propagation delay) of a 74AS74 with a pull-up resistor? Does the pull-up resistor jeopardize the 74AS speed advantages vs 74HC?

A pull up resistor can also introduce more noise if you have a noisy Vcc, to accurately determine the phase noise a simulation would be best.

3) at the end: to minimise jitter driving a CMOS is correct that any 74AS with pull-up resistor is better of any 74HC device?

There is no specification for jitter in the datasheets of these devices, so it will need to be measured. You can however understand the sources of jitter and work to eliminate them:

These jitter sources include:

Thermal noise

  • kTB noise, which is associated with electron flow in conductors and increases with bandwidth, temperature, and noise resistance

  • Shot noise: electron and hole noise in semiconductors in which the magnitude is governed by bias current and measurement bandwidth

  • Pink noise: noise that is spectrally related to 1/f

Source: https://www.radio-electronics.com/articles/circuit-design/understanding-measuring-jitter-in-electronic-194

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  1. Which is the lowest safer pull-up resistor for a 74AS piloting a CMOS device? Websites recommends from 10 kΩ to 2.2 kΩ from TTL to CMOS. I would use 1 kΩ. Is it 470 Ω still safe and better?
  2. The 74HC74 runs at 30 Mhz, the 74AS74 runs at 100 Mhz. But which is the maximum speed (or propagation delay) of a 74AS74 with a pull-up resistor? Does the pull-up resistor jeopardise the 74AS' speed advantages vs the 74HC?

I suggest sticking to the recommended range of pull-up resistance values. 74ASxx family of logic gates is based on BJT "Schottky" transistor. Below is the internal structure of 74AS00 NAND gate.

![enter image description here

The circled NPN is the high output driving transistor. It can drive the output to high very quickly, but obviously the max voltage it can get is around \$V_{CC}-0.6\$ due to base-emitter forward bias drop. To allow the output to reach the power rail, you need an external pull-up. If the output is fed to a load, then according to the specs, the output voltage is guaranteed to not drop below \$V_{CC} - 2\$ regardless whether the pull-up is present or not (provided that you don't violate the maximum current draw). But, if the output is fed to an input of a CMOS logic gate, which has very very high impedance (i.e., drawing no current), then surely it will reach \$V_{CC}\$ if the pull-up is present. Supposed \$V_{CC}=5V\$, then 74AS74 is able to drive the output voltage up to ~4.4V under 7.5ns (assuming the input capacitance of the CMOS is ~7pF, i.e, <50pF). This voltage is well above the minimum high−level input voltage, \$V_{IH}\$, of the 74HCxx logic gate. Hence, whether you have a pull-up or no pull-up at the output of the 74AS74 makes no difference.

  1. To minimise jitter driving a CMOS: is it correct that any 74AS with a pull-up resistor is better than any 74HC device?

I don't quite understand your question. But, I am guessing that you are asking if adding a pull-up resistor on the output of 74AS will give you a smaller jitter than the 74HC device. If that is your question, then my take is "I don't think so". Jitter has nothing to do with the pull-up, but it might be affected by dynamic capacitive and resistive loading and perhaps temperature. My bet is the jitter is minimal if you are feeding into a CMOS. You can find out yourself by experimenting.

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