Using 2 Data Flip Flops to create an up counter from 0 to 3 and repeats

Question

I've done most of the legwork. I've got this design working using 2 set reset(SR) flip flops, but I need to make it using 2 data flips, a.k.a D flip flops.

What I did:

Note the numbers not in brackets are in base 10, the numbers in brackets are in base 2.

State Diagram

Note the truth table for a set(S) reset(R) flip flop.

S R |   Q(output)   |     !Q
----+---------------+--------------
0 0 | no change     | no change
0 1 | 0             | 1
1 0 | 1             | 0
1 1 | indeterminate | indeterminate
    | (sometimes 0, | (sometimes 0,
    |  sometimes 1) |  sometimes 1)

• Present State is represented by P.S,
• Next State is represented by N.S,
• A is my most significant bit of input
• B is my least significant bit of input,
• x represnts don't care,
• ! represent not

---

P. S | N. S |  A  |   A   |  B  |   B
A  B | A  B | Set | Reset | Set | Reset
-----+------+-----+-------+-----+-------
0  0 | 0  1 |  0  |   x   |  1  |   0
0  1 | 1  0 |  1  |   0   |  0  |   1
1  0 | 1  1 |  x  |   0   |  1  |   0
1  1 | 0  0 |  0  |   1   |  0  |   1

Through K-Map I got:

• Set of A = !A and B,
• Reset of A = A and B,
• Set of B = !B,
• Reset of B = B

This is my design using 2 SR flip flops:

If someone could help me create a circuit with the same functionality except using 2 D flip flops, that would be greatly appreciated.

Answer 1

You just need to apply the same technique, but substitute the truth table for a DFF where you have the SRFF. Instead of separate equations for A Set, A Reset, etc., you'll have two equations — one for the D input of A and one for the D input of B.