The goal of this project to design a computational lock alarm in Verilog to be run on an Altera board (note on the board 0 is actually ON and 1 is OFF).
Based on the design criteria I created a state diagram of all possible states and contained them into a "cases" statement in my verilog code.
However, I'm having trouble comparing the inputted combination code and the registered password and ALSO rewriting a new password to the registered password when the design is in a particular state.
Note that I've included many of my troubles in comment blocks/lines.
/* NOTES: FIX THE PASSWORD REGISTER AND INPUTS*/
module combinationalLock (clock, INPUTS, enter, change, reset, door, newPass, alarm);
input enter, change, reset;
input [4:1] INPUTS; // I don't know if I've defined this correctly
output door, newPass, alarm;
reg[3:1] y, Y;
wire[4:1] passwordREG; // rewritable and comparable to INPUTS (I don't know if I've defined this correctly)
parameter[3:1]
// Binary state values
START = 3'b000,
AGAIN = 3'b001,
ALARM = 3'b010,
CHANGE_OLD = 3'b011,
OPEN_DOOR = 3'b100,
CHANGE_OLD_AGAIN = 3'b101,
CHANGE_NEW = 3'b110;
// Default password combo
passwordREG = 4'b0110; // IM TRYING TO SET THE DEFAULT PASSWORD HERE
// State conditions and changes
always @(INPUTS, y, reset, change, enter)
case(y)
START: if((enter == 0) && (/*INPUTS ARE EQUAL TO REGISTRED PASSWORD*/)) Y = OPEN_DOOR;
else if ((enter == 0) && (/*INPUTS ARE NOT EQUAL TO REGISTRED PASSWORD*/)) Y = AGAIN;
else Y = START;
AGAIN: if((enter == 0) && (/*INPUTS ARE EQUAL TO REGISTRED PASSWORD*/)) Y = OPEN_DOOR;
else if ((enter == 0) && (INPUTS != passwordREG)) Y = ALARM;
else Y = AGAIN;
ALARM: if(reset == 0) Y = CHANGE;
else Y = ALARM;
CHANGE_OLD: passwordREG = 4'b0110;
if((change == 0) && (/*INPUTS ARE EQUAL TO REGISTRED PASSWORD*/)) Y = CHANGE_NEW;
else if ((change == 0) && (/*INPUTS ARE NOT EQUAL TO REGISTRED PASSWORD*/)) Y = CHANGE_OLD_AGAIN;
else Y = CHANGE_OLD;
OPEN_DOOR: if(enter == 0) Y = START;
else Y = OPEN_DOOR;
CHANGE_OLD_AGAIN: if((change == 0) && (/*INPUTS ARE EQUAL TO REGISTRED PASSWORD*/)) Y = CHANGE_NEW;
else if ((change == 0) && (/*INPUTS ARE NOT EQUAL TO REGISTRED PASSWORD*/)) Y = ALARM;
else Y = CHANGE_OLD_AGAIN;
CHANGE_NEW: passwordREG = INPUTS; // NOTE IN THIS LINE IM TRYING TO REWRITE THE REGISTERED PASSWORD
if((CHANGE == 0)||(ENTER == 0)) Y = START;
else Y = CHANGE_NEW;
default: Y = 3'bxxx;
endcase
// Clock pulse
always @(posedge clock)
y<=Y;
// Output
assign door = (y == OPEN_DOOR);
assign newPass = (y == CHANGE_NEW);
assign alarm = (y == ALARM);
endmodule
Note: I'm also getting some odd syntax errors at line 27, 47, and 59 where they expect an "end case".