I have a design which after synthesis at clock 500 picoseconds in dc_shell takes about 2 minutes to run the synthesized netlist against the testbench. The synthesized netlist worked as expected.

After that, I reduced the clock period to 400 ps and synthesized again. Timing is met again with a slack 0.43. This new netlist just took 10 seconds to complete the simulation and all the results are x.

Why is that dc_shell says timing is MET but the simulation is too fast and the results are x. Can someone please enlighten me on this?

  • \$\begingroup\$ Can you share your testbench code? \$\endgroup\$ – The Photon Nov 12 '18 at 1:25
  • \$\begingroup\$ @ThePhoton Please have a look at this file. drive.google.com/file/d/1eeMiiJeonFQ2yv7sbBkJDHk7EScVUgWt/… The image and kernel files referred are just text files containing the hexadecimal values of the image. \$\endgroup\$ – user3219492 Nov 12 '18 at 1:33
  • \$\begingroup\$ @ThePhoton I would like to add one more thing. MY initial design did not have input_addr_next_testing, output_addr_next_testing in I/O port declaration. Durin that time all my results were x even at 500 ps. When I added these ports to debug, the synthesized netlist started producing proper results. If I remove them, again the results are x. Basically output_addr_next_testing is input of a flip flop and input_addr is output of the ff. Similarly for output_addr_next_testing. IT is too wierd. \$\endgroup\$ – user3219492 Nov 12 '18 at 5:35
  • \$\begingroup\$ @ThePhoton I solved the issue...Just now had the time to post the answer \$\endgroup\$ – user3219492 Dec 25 '18 at 9:06

DC_Compiler seems to have an issue in synthesizing the reset signal of the synchronous flipflops in some cases.

Just adding this compiler directive inside my flipflop module solved the issue: //synopsys sync_set_reset "rst"

Here rst is the name of reset signal of my DFF.

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