I have a design which after synthesis at clock 500 picoseconds in dc_shell takes about 2 minutes to run the synthesized netlist against the testbench. The synthesized netlist worked as expected.
After that, I reduced the clock period to 400 ps and synthesized again. Timing is met again with a slack 0.43. This new netlist just took 10 seconds to complete the simulation and all the results are x.
Why is that dc_shell says timing is MET but the simulation is too fast and the results are x. Can someone please enlighten me on this?